Abstract: A technique for self-aligned processing of semiconductor device features is disclosed. This technique includes the formation of a semiconductor device with features extending from the plane of a semiconductor substrate. The features may include polysilicon transistor gates. A coating is deposited on the features and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a surface of the features without lithographic processing. In one form, the exposed surface of the feature is defined by a polysilicon member, and the polysilicon member is at least partially selectively removed and replaced with a metal.

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual photoresist layer as a mask. The undoped polysilicon layer is etched by using the residual photoresist layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: A field effect transistor includes a semiconductor substrate; a gate insulating film on the semiconductor substrate; a first impurity region and a second impurity region formed in a surface of the substrate; an lightly doped region in contact with the first impurity region and formed toward the second impurity region in the semiconductor substrate; and an L-shaped gate electrode on the semiconductor substrate extending between the lightly doped region and the second impurity region.

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract: The formation of a spacer for a graded dopant profile having a triangular geometry is disclosed. In one embodiment, a method has three steps. In the first step, a gate is formed on a substrate, the gate having two edges. In the second step, at least one spacer is formed, where each spacer is adjacent to an edge of the gate and has a triangular geometry. In the third step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer.

Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask.

Abstract: A silicon dioxide film with a film thickness of 250 to 310 nm is formed on a conductive layer. A resist coated on the silicon dioxide film is exposed with an i-line in a wiring pattern, and developed to form the wiring pattern on the resist. The silicon dioxide film and the conductive layer are simultaneously processed using this resist as a mask. As a result, formation of tails in the resist can be suppressed, while a dielectric breakdown voltage across a conductive layer above the silicon dioxide film and the conductive layer below the silicon dioxide film is ensured, and an increase in step is suppressed. A wiring layer having a desired line width can be formed with high controllability.

Abstract: A method for preventing the diffusion of dopants in a dual gate device includes the steps of providing a semiconductor substrate having wells and isolating structures thereon, and then forming a gate oxide layer over the well regions. Thereafter a polysilicon layer is formed over the gate oxide layer, and then a first conductive layer is formed over the polysilicon layer. Subsequently, a plasma treatment using gaseous nitrogen or gaseous ammonia is conducted to form a barrier layer. Finally, a second conductive layer is formed over the barrier layer.

Abstract: A method of making N-channel and P-channel IGFETs is disclosed.

Abstract: A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.

Abstract: A method for manufacturing a flash memory. A substrate having a patterned pad oxide layer formed thereon and a patterned mask layer on the pad oxide layer is provided. A doped region is formed in the substrate exposed by the patterned mask layer and the pad oxide layer. A spacer is formed on the sidewall of the patterned mask layer and the pad oxide layer to cover a portion of the doped region. A trench is formed in the substrate exposed by the mask layer and the spacer. An insulating layer is formed to fill the trench, wherein the insulating layer leveled with a top surface of the patterned mask layer. The patterned mask layer and the spacer are removed to respectively expose the patterned oxide layer and the portion of the doped region. A self-aligned tunnel oxide layer is formed on the portion of the doped region. A patterned first conductive layer is formed over the substrate to expose portions of the patterned pad oxide layer above the substrate excluding the doped region.

Abstract: A method of manufacturing liquid crystal display (LCD), comprising the steps of: forming a bottom indium tin oxide (ITO) in a pixel area of a transparent insulating substrate; forming a gate line and a storage line spaced with each other, the storage line including a first part having a first width and a second part having a second width, the second part is formed in the central portion of the pixel region and the first part is formed in the both sides of the second part and is directly contacted with the bottom ITO; depositing a gate insulating layer over the entire surface of the substrate; forming a semiconductor layer on the gate insulating layer over the gate line; forming a data line being in perpendicular to the gate line, source and drain electrodes being overlapped with both side portions of the semiconductor layer and a conductive pattern being disposed over the second part of the storage line; depositing an organic insulating layer having lower dielectric constant on the entire surface of the subst

Abstract: A method of forming a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device on a semiconductor substrate with reduced masking steps is disclosed. In the first method, the reduced masking steps are arranged in an optimal sequence in which the gate layer is patterned first as a self-aligned mask. The gate layer includes a plurality of gate segments separated by spacings. An active mask for defining active body regions is then patterned in the spacings of the gate layer to form a combination mask. Using the combination mask as a shield, body and source regions are ion-implanted into the substrate. During the formation of the active mask, remnant material of the active mask adheres to the boundaries of the gate segments to form a spacer layer which is utilized to alleviate the cell-to-cell encroachment problem due to the side diffusion effect of the body and source regions.

Abstract: A method for avoiding interference in a CMOS sensor. A substrate at least comprising a CMOS sensor, an interconnect layer and an inter-layer dielectric layer thereon is provided. A passivation layer is formed over the substrate. A photolithography and etching process is performed to remove a part of the passivation layer and a part of the inter-layer dielectric layer above a sensor region of the CMOS sensor. The sensor region is thus exposed. An oxide layer is formed on the exposed sensor region. A micro-lens is formed on the oxide layer.

Abstract: An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Abstract: An improved method for fabricating an ESD protection device so as to avoid ESD damage to a wafer. The improved method includes simultaneously forming an internal circuit and the ESD protection device without additional photomask or other process. The improved method uses a P.sup.+ doped region to take the place of an N.sup.- doped region of an interchangeable source/drain region with a LDD structure for the ESD protection device, of which its trigger voltage is adjusted by simply varying the P.sup.+ concentration.

Abstract: A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.