Abstract: A trench is formed on the surface of a semiconductor substrate. An oxide film is then formed on the side wall portion and the bottom portion of the trench, ions are implanted at least in the side wall portion of the trench for preventing an impurity from passing through there. Thereafter the ion-implanted portion is subjected to a heat treatment, whereby an impurity passing-through preventing film is formed between the bulk of the semiconductor substrate and the oxide film.

Abstract: The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first conductive layer formed in the semiconductor substrate using a dopant, and being of a second conductivity type, a silicon-rich nitride film formed on the first conductive layer, and a second conductive layer formed on the silicon-rich nitride film, wherein the silicon-rich nitride film inhibits outdiffusion of dopant from the first conductive layer into the second conductive layer, and blocks interdiffusion between the second conductive layer and the first conductive layer.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide.

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

Abstract: A method for forming a sub-quarter micron MOSFET having an LDD structure is described. An active area is provided in a semiconductor substrate separated from other active areas by isolation regions. Ions are implanted into the semiconductor substrate in the active area wherein a heavily doped region is formed adjacent to the surface of the semiconductor substrate and wherein a lightly doped region is formed underlying the heavily doped region. A first dielectric layer is deposited overlying the semiconductor substrate in the active area. The first dielectric layer is etched away to form an opening to the semiconductor substrate. The semiconductor substrate within the opening is etched through to form a partial trench in the semiconductor substrate. Spacers are formed on the sidewalls of the first dielectric layer within the opening. A layer of conducting material is deposited over the first dielectric layer and the spacers and within the opening.

Abstract: A method for forming a copper interconnect (54) begins by depositing a barrier layer (48). An intermediate layer (50) is formed over the barrier layer (48) by exposing the barrier layer (48) to a plasma silane environment. The layer (50) is conductive when deposited so that contact resistance is not affected. The layer (50) is insitu covered with a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20) thereby exposing a portion (50a) of the layer (50). This portion (50a) will natively oxidize in a room ambient to form a copper electroplating prevention barrier whereby copper will not electroplate in the region (20). Therefore, the region (50a) prevents barrier-to-copper interfaces to avoid delamination of the copper while preserving the edge exclusion region desired for copper electroplating.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as an anti-reflective coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the oxide layer are patterned to form ultra short channel polysilicon gates. A thermal annealing is performed to recover the etching damage in the substrate and generate a pad oxide layer on the surface of the polysilicon gate and the substrate. An nitrogen-doped amorphous silicon layer is formed on the gate structure and on the pad oxide. Next, an ion implantation is carried out to dope dopants into the gate and substrate, thereby forming source and drain. A steam oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon dioxide layer.

Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration.

Abstract: An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.

Abstract: A method for manufacturing a buried transistor, which includes the steps of forming a field oxide layer in a substrate, the field oxide region having a central portion having a greater thickness than opposite edge portions thereof, forming source/drain regions in the substrate, on opposite sides of the field oxide layer, removing the field oxide layer, and forming a gate electrode on the resultant structure.

Abstract: The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them.

Abstract: The method of the present invention includes forming a silicon dioxide layer. A polysilicon layer is then deposited on the silicon dioxide layer. Next, a gate structure is formed by etching. A silicon oxynitride layer is formed on the substrate and covers the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and top of the polysilicon gate. Then, the source and the drain are formed. A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed to form air gaps between the gate and the side-wall spacers.

Abstract: A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: A substrate (10) of a semiconductor device includes a power section (12) and a control section (14). The power section includes doped regions (16, 18, 20) and terminals (22, 24, 26) which define power devices such as transistors or SCRs. The control region also includes doped areas including a parasitic collector (32). A minority carrier current (62) flows from the doped regions of the power section to the collector of the control section when the power device to substrate junction is forward-biased. A self-biased moat assembly (40) includes a first doped region (42) between the doped regions of the power and control sections under which the parasitic minority carrier current flows. An electrical connection (46) connects the moat first doped region (42) with a moat second doped region (44). The self-biased moat assembly is isolated from ground such that it is self-biased negative in accordance with internal operating conditions of the semiconductor device.

Abstract: A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.