Abstract: An ONO layer 18 located vicinity of a transistor TR1 for programming is removed. A floating gate FG1 of the transistor TR1 is formed by carrying out etching of a polysilicon layer 16. Then, an inter-layer film SM1 of the transistor TR1 is formed by carrying out oxidation process. The inter-layer film SM1 is formed so as to cover the floating gate FG1. Arsenic is implanted ionically into a semiconductor-substrate 12 using the floating gate FG1 and the inter-layer film SM1 as a mask. Ions of the arsenic thus implanted do not pass through the inter-layer film SM1 and are stopped at the surface. Because the inter-layer film SM1 is made of a silicon oxidation layer formed relatively thick. So that, the inter-layer film SM1 maintains its charge-storage characteristic originally owns even when the ion implantation is carried out.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.

Abstract: A semiconductor process includes forming a spacer support structure on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. A. The spacer support structure includes a substantially vertical sidewall that is laterally aligned over a boundary between the first source/drain region and the channel region of the semiconductor substrate. A gate dielectric is then grown and a transistor gate fabricated by forming a first spacer structure on the sidewall of the spacer support structure. The first spacer structure includes a substantially vertical first sidewall in contact with the spacer support structure sidewall and further includes a second sidewall that is laterally aligned over a boundary between the channel region and the second source/drain region of the semiconductor substrate.

Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.

Abstract: A method for fabricating a semiconductor device having LDD structure. The method includes: a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate; a second step for forming a conductive layer on said insulating layer; a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer; a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer; a fifth step for forming heavilyly doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer; a sixth step for removing said patterned photoresist layer; and a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

Abstract: Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed.

Abstract: A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

Abstract: A process for creating a crown shaped storage node structure, for a DRAM capacitor structure, featuring the use of a silicon oxynitride layer, underlying the crown shaped storage node structure, has been developed. A silicon oxynitride layer is placed overlying the interlevel dielectric layers that used to protect underlying DRAM elements, and placed underlying a capacitor opening in an overlying insulator layer. A selective RIE procedure is used to create the capacitor opening, in an insulator layer, with the RIE procedure terminating at the exposure of the underlying silicon oxynitride layer. After creation of the crown shaped storage node structure, in the capacitor opening, overlying the silicon oxynitride layer at the bottom of the capacitor opening, the insulator layer used for formation of the capacitor opening, is selectively removed from the regions of silicon oxynitride layer, not covered by the overlying crown shaped storage node structure, using wet etch procedures.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed.

Abstract: A fabrication method for high voltage power devices with at least one deep edge ring includes the steps of growing a lightly doped N-type epitaxial layer on a heavily doped N-type substrate, growing an oxide on the upper portion of the epitaxial layer, masking and then implanting boron ions, etching the oxide to expose regions for aluminum ion implantation, forming a layer of preimplantation oxide, masking of the body regions with a layer of photosensitive material and implanting aluminum ions, and a single thermal diffusion process forming a layer of thermal oxide on the epitaxial layer and simultaneously forming at least one deep aluminum ring and an adjacent body region doped with boron.

Abstract: A semiconductor device comprising a package formed of a thermoplastic resin, first and second lead frames arranged parallel to each other with a predetermined space interposed therebetween, and each having a distal end portion of a predetermined length located in the package, solder films formed on the first and second lead frames from outside the package to inside the package, a semiconductor element mounted on the distal end portion of the first lead frame and having an electrode, and a bonding wire having an end connected to the electrode of the semiconductor element, and another end connected to the distal end portion of the second lead frame.

Abstract: Disclosed is a three-dimensional integrated memory cell having a high interior volume and a method for constructing the same. The cell makes use of a highly conductive substrate material for the bottom electrode, allowing construction of a thin substrate without intolerable resistance. The substrate of the preferred embodiment, for example, comprises titanium silicide. The preferred method comprises conformal deposition of a thin polysilicon layer within a high aspect ratio container, followed by deposition of a suitable metal for silicidation with the polysilicon layer. The metal need not be conformal for this preferred method and may be deposited by sputter deposition. After silicidation, excess metal is selectively etched away to leave a conformal, thin yet highly conductive substrate material.

Abstract: A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

Abstract: A semiconductor device having memory cells, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS transistors is formed in a process that allows the same low-voltage device parameters to be used regardless of whether the low-voltage transistors are formed with or without the memory cells and the high-voltage CMOS transistors.

Abstract: The method of the present invention is a method of including forming a gate oxide layer on the substrate. A polysilicon layer is formed on the gate oxide layer. Then, a photographic and etching steps are used to form a gate structure. An oxidation is performed on the substrate and the gate structure to form an first oxide layer on the substrate and on the surface of the polysilicon gate. A silicon nitride layer is deposited on the first oxide layer. A side-wall spacers is formed on the side walls of the gate structure, a first portion of the first oxide layer remaining between the gate structure and the side-wall spacers, and a second portion of the first oxide layer remaining under the side-wall spacers. Next, a first ion implantation performed into the substrate to form first doped ions regions to serves as source and drain region of the transistor. Then, the side-wall spacers is removed, therefore remained the second portion of the first oxide layer covered by the side-wall spacers.

Abstract: A semiconductor chip having electrode terminals arranged in an area-array manner is mounted on an upper surface of a first region of a circuit board. Bonding pads are provided on the upper surface of a second, different region of the circuit board, and are connected to electrode terminals on the upper surface of the chip with bonding wires covered with an electro-insulation coating. External connection terminals provided on an opposing surface of the second region of the circuit board in an area-array manner are electrically connected to the bonding pads by conductive vias provided through the circuit board in the thickness direction. An electro-insulation film covers the chip, including the bonding wire/electrode terminal connections, and the upper surface of the second region of the circuit board. An electro-conductive resin encapsulates the coated bonding wires and the electro-insulation film.

Abstract: The invention is a method for fabricating a capacitor in a dynamic random access memory. The capacitor has double cylinder structure and is fabricated by utilizing an insulating side wall spacer to pre-define the capacitor structure. Then, a wet etching process is applied to remove the insulating side wall spacer and expose a surface of a structured lower electrode. Then, a dielectric thin film and an upper electrode are formed over the surface of the lower electrode sequentially to form the capacitor.

Abstract: The present invention is intended to provide, in MOS transistors used as a bonding layer for silicon regions of an SOI substrate, an nMOS transistor on a silicon region of an SOI substrate which uses a polycrystalline silicon layer as a layer to be bonded with the silicon substrate and a pMOS transistor on another silicon region of the SOI substrate and electrically isolated back gate electrodes through a back gate insulation film on the silicon region side between the silicon regions and a polycrystalline silicon layer. A leak current is reduced and a malfunction of the transistors is eliminated by providing pickup electrodes for the back gate electrodes.