Abstract: A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

Abstract: An EEPROM semiconductor structure is produced with a resistor, a thin-film transistor, a capacitor, and a transistor. The individual implantation steps are utilized to create various structures and, as a result, the production process is substantially simplified.

Abstract: A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer.

Abstract: Methods of forming power semiconductor devices include the steps of forming an insulated gate electrode on a face of semiconductor substrate containing a body region of first conductivity type (e.g., P-type) therein extending to the face. Using the gate electrode as a mask, a step is then performed to oxidize the body region and substrate at the face to form a first oxide layer. Source and drain region dopants are then implanted through the first oxide layer and into the body region and substrate to define recessed source and drain regions of second conductivity type therein, respectively. The step of implanting source and drain region dopants may be preceded by the step of etching the first oxide layer using an etching mask which covers the gate electrode. The step of oxidizing the body region and substrate may also be preceded by the step of forming nitride spacers on sidewalls of the gate electrode and then also using the nitride spacers as a mask during the oxidation step.

Abstract: A new structure of a capacitor for a DRAM is disclosed herein. The structure of the capacitor includes a mushroom shape first storage node, a dielectric layer and a second storage node. The mushroom shape first storage node includes a base portion that is formed of polysilicon. A plurality of mushroom neck portions located on the base portion. A plurality of roof portions are connected on the tops of the mushroom neck portions. The dielectric layer is conformally covered the surface of the mushroom shape storage node. The second storage node encloses the surface of the dielectric layer. The formation of the mushroom shape capacitor includes forming a first conductive layer over a wafer. Then, an undoped hemispherical grains silicon (HSG-silicon) is formed on the first conductive layer. The HSG-silicon is separated along the grain boundaries to expose a portion of the first conductive layer. Next, the exposed first conductive layer is etched by using the HSG-silicon layer as a mask.

Abstract: The present invention provides a method for stabilizing the crystal structure of a silicon substrate after an ion implantation process including the step of exposing the substrate to a temperature not higher than 200.degree. C. for a time period of not less than 10 seconds, and preferably to a temperature between about 100.degree. C. and about 200.degree. C. for a time period of between about 10 seconds and about 10,000 seconds.

Abstract: A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.

Abstract: Making low resistance contact between two silicon layers has been accomplished by implanting nitrogen ions into a freshly formed silicon surface thereby forming a nitrogen rich layer at the surface which suppresses formation of a surface layer of oxide, the normal 20-30 Angstrom thick native oxide being now restricted to 3 or 4 Angstroms. When a layer of polysilicon is deposited onto this nitrided surface good, low resistance electrical contact is made. The process is fully compatible with existing methods for the manufacture of integrated circuits. An example of its application to making low resistance contact to a FET gate electrode is given.

Abstract: A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity .alpha.6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer is epitaxially grown on the substrate layer. A steep-walled groove is etched through the n+ SiC layer and partially into the p SiC layer at a location on the substrate where a MOSFET gate structure is desired. Subsequently, a thin layer of silicon dioxide and a layer of gate metal are successively deposited over the entire structure. The gate metal layer is deposited with sufficient thickness to substantially fill the groove. A layer of photoresist is applied to the entire surface of the gate metal layer. The photoresist and the underlying gate metal are then reactive ion etched down to the oxide layer, leaving gate metal remaining only in the groove.

Abstract: A method is disclosed for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The MEM device can be fabricated within a substrate cavity and encapsulated with a sacrificial material. This allows the MEM device to be annealed and the substrate planarized prior to forming electronic circuitry on the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the electronic circuitry can be protected by a two-ply protection layer of titanium nitride (TiN) and tungsten (W) during an etch release process whereby the MEM device is released for operation by etching away a portion of a sacrificial material (e.g. silicon dioxide or a silicate glass) that encapsulates the MEM device. The etch release process is preferably performed using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCI) which reduces the time for releasing the MEM device compared to use of a buffered oxide etchant.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

Abstract: The low-voltage, e.g., 2.5-volt, transistors that support the logic operations of a CMOS device are formed to have a thin layer of gate oxide, while the high-voltage, e.g., 3.3 or 5-volt, transistors that support the analog operations of the device are formed to have a thick layer of gate oxide in a cost-effective process flow that requires only one additional masking step over a conventional double-poly CMOS process.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: A method for manufacturing sensors using semiconductors that is optimal for obtaining compact sensors is described. The method includes the steps of (a) applying an n-type silicon layer to the upper surface of a silicon substrate, (b) applying a p-type silicon layer on either the upper surface of the n-type silicon layer or the upper surface of a base, (c) removing part of the p-type silicon layer by electrochemical etching, (d) joining the base with the p-type silicon layer applied to the n-type silicon layer or joining the n-type silicon layer with the p-type silicon layer applied to the base, (e) removing the silicon substrate and exposing the upper surface of the n-type silicon layer, and (f) forming a strain gage in a section of the upper surface of the silicon substrate so that a portion of the n-type silicon layer facing the upper surface of the base functions as a diaphragm.

Abstract: An oxide film is deposited on a semiconductor substrate on which a field oxide film and a gate electrode are formed. The oxide film is etched back to form a first sidewall insulating film made of the oxide film on a side surface of the gate electrode. Then a silicon film is selectively grown on the gate electrode and on the semiconductor substrate. Thereafter a thermal oxide film is formed on a surface of the silicon film by thermally oxidizing. In the step of thermal oxidation, a thin silicon film deposited on a part of the first sidewall insulating film and a part of the field oxide film is fully oxidized. Thereafter, the thermal oxide film is etched back and thereby a second sidewall insulating film made of the thermal oxide film is formed on a side surface of the silicon film.

Abstract: A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Abstract: N-channel and P-channel transistor performances are separately optimized by activating the source/drain regions of the N-channel transistor before forming the P-channel lightly doped implant. Separate sidewall spacers for the moderately or heavily doped implants of the N- and P-channel transistors are employed. Embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors.

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.