Abstract: A structure and method of fabrication is provided for a micromechanical overrange protected pressure sensor. A pressure sensor having a silicon substrate is provided with a cavity and a deformable diaphragm wherein deflection of the diaphragm in response to pressure is limited by a forward pressure stop. A method is provided for electrodepositing a metal layer which is attached to the substrate adjacent to the diaphragm to provide a reverse pressure stop in response to pressure supplied to the underside of a diaphragm. The metal layer has a relatively low thermal coefficient of expansion and is patterned through use of a photo-resist layer. A previously deposited precision spacer between the diaphragm and reverse pressure stop is removed to provide a precision gap between the reverse pressure stop and the diaphragm.

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract: A vertical type semiconductor device having a semiconductor substrate and at least one gate electrode structure formed in the semiconductor substrate for controlling a current flow across the semiconductor substrate. The semiconductor substrate is formed by a silicon substrate, a silicon carbide or diamond layer epitaxially deposited on the silicon substrate, and a silicon layer epitaxially deposited on the silicon carbide or diamond layer. Recesses are formed in the silicon layer and gate electrodes are provided in the recesses via silicon oxide films. Source or emitter regions are formed in portions of the silicon layer which are brought into contact with the silicon oxide films by inverting the conductivity of these portions. Source or emitter electrodes are provided on the source or emitter regions, and a drain or collector electrode is provided on a rear surface of the silicon substrate.

Abstract: A method (50) for designing a semiconductor device (10). The method (50) has an annealing step (59). In the annealing step (59), the semiconductor device (10) is annealed in an ambient containing oxygen. The oxygen has a partial pressure of greater than 11.85 Torr. The annealing step (59) results in a reduction of uncontrolled doping from the gate electrode (33) of the semiconductor device (10) to the channel region of the semiconductor device (10).

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.

Abstract: A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Abstract: There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the high-speed operation and high reliability can be used as a resistance element, the process margin can be increased without increasing the number of manufacturing steps, and defects due to leakage between the resistance element and the underlying substrate can be eliminated so as to ensure the high manufacturing yield. In a semiconductor device having a conductive film formed over the surface of a semiconductor substrate with a first insulating film disposed therebetween and a metal wiring layer connected to the conductive film via a contact hole formed in a second insulating film which is formed on the conductive film, an etching stopper film having a selective etching ratio with respect to the second insulating film is formed in an area directly below the contact hole with a third insulating film disposed therebetween.

Abstract: A novel structure of TFT is described. In the structure of TFT, an anodic oxidation film, which is a material composing a gate electrode, is laid at the side of gate electrode. An electrode, which is connected to a source, drain region, is in contact with the upper surface and the side of the source, drain region, and extended on the upper surface of an insulation film which is laid on the gate electrode. In the preparation process of TFT, it can be completed by using only two sheets of mask.

Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.

Abstract: For a semiconductor device having a silicide protection film, provided is a semiconductor device fabrication method which prevents problems caused by overetching when forming the silicide protection film. A silicon oxide film (8) is formed all over the surface in a protection region (PR) and in an ordinary region (OR). Then N-type impurities are introduced by an ion implantation from above the silicon oxide film (8) through the silicon oxide film (8) to form a source/drain region (7) in a self-aligned manner in the surface of an SOI layer (3).

Abstract: A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed between the sidewalls. The thickness of the spacer structure is preferably in the range of approximately 0.04 microns. A masking layer is formed on an upper surface of a semiconductor substrate. The masking layer includes first and second masking structures and a channel trench material. Opposing sidewalls of the first and second masking structures are laterally displaced by a channel displacement. The opposing sidewalls together with an upper surface of the semiconductor substrate define a channel trench. The channel trench is displaced above and aligned with a channel region of the semiconductor substrate. The channel trench material fills the channel trench.

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed over the substrate. A first silicon layer is then formed over. A buried contact opening is defined through the first silicon layer and the gate insulator layer extending down to the substrate. The substrate is then doped for forming a buried contact region. Next, a second silicon layer and a masking layer is formed. A shielding opening is then defined through the masking layer and the second silicon layer to a portion of the buried contact region. At the same time, an upper gate electrode and an interconnect are defined by removing a portion of the second silicon layer. A shielding layer is formed in the shielding opening over the buried contact region. A lower gate electrode is then defined by removing a portion of the first silicon layer.

Abstract: A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantation of dopant into trench sidewalls creates channel regions oriented at an angle relative to the horizontal bit lines. Disposing successive diffused bit lines in vertically separated planes enables fabrication of ROM cells having full channel lengths which occupy a smaller surface area. Tilted ion implantation may be utilized to introduce dopant into channel regions.

Abstract: A trenched gate MOSFET (metal oxide semiconductor field effect transistor) structure is fabricated via a novel process which includes the step of using a common mask serving the dual role as a mask for the body layer formation and as a mask for trench etching. The common mask defines an patterned oxide layer which includes a plurality of openings at a predetermined distance away from the scribe line of the MOSFET structure. During fabrication, material of the body layer is implanted through the openings of the patterned oxide layer. Thereafter, the implanted material is side-diffused and merged together under a drive-in cycle as one continuous body layer. Using the same patterned oxide layer as a shield, trenches are anisotropically etched in the substrate. The MOSFET structure as formed requires no separate mask for delineating the active body region away from the scribe line, resulting reduction of fabrication steps. The consequential benefits are lower manufacturing costs and higher production yields.

Abstract: A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.

Abstract: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of microcrystalline silicon carbide particles. The microcrystalline silicon carbide particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

Abstract: A method for forming a DRAM capacitor that utilizes silicon nitride spacers on two occasions to perform self-aligned contact window etching operations. Furthermore, on the second etching operation, one less photomask is required for the etching of the second via. In addition, a silicon nitride layer over the first polysilicon layer has a smaller thickness than the usual oxide layer in a conventional method of manufacture. Consequently, a shallower contact step height for the capacitor, which is beneficial to the production of miniaturized devices, is obtained. Finally, the tri-fork shaped capacitor structure further increases the surface area of the capacitor so that the capacitance of the DRAM capacitor is increased.

Abstract: The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.

Abstract: A method for forming wells of a semiconductor device, comprising the steps of forming a plurality of field insulating layers on a field region of a semiconductor substrate; forming first impurity regions of a first conductive type at a first depth beneath a surface of the semiconductor substrate; forming first impurity regions of a second conductive type beneath the surface of the semiconductor substrate at a second depth between the field insulating layers; selectively forming second impurity regions of the second conductive type in the first impurity regions of the first conductive type between adjacent field insulating layers; forming second impurity regions of the first conductive type in the first impurity regions of the second conductive type at both sides of the second impurity regions of the second conductive type; and diffusing the first and second impurity regions of the first conductive type and the first and second impurity regions of the second conductive type by a drive-in process to form a firs

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.