Abstract: An electrical power distribution system includes a plurality of circuit protection devices coupled between an electrical power source and a plurality of electrical loads. Each circuit protection device includes a trip unit, a network interface communicatively coupled to a communication network including the circuit protection devices, a processor, and a memory. The memory stores instructions that, when executed by the processor, cause the processor to store test operational parameters associated with the circuit protection device, receive a test message including test data representing an electrical condition in the electrical power distribution system, adjust the test operational parameters based on the test data to simulate a response of the trip unit to the electrical condition, generate circuit protection data based on the test data and the adjusted set of test operational parameters, and transmit the circuit protection data to at least one of the communication network and a remote access device.

Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a light-emitting diode (LED) includes a substrate, a carrier confinement (CC) region positioned over the substrate, and an active region position over the CC region. The CC region includes a first CC layer comprising aluminum gallium nitride and a second CC layer position over the first CC layer. The second CC layer also includes aluminum gallium nitride. The active region is configured to have a transient response time of less than 500 picoseconds (ps).

Abstract: Embodiments of a system and a method for evaluating a joint compound specimen can be used to determine a numerical sandability value for the specimen. A moving assembly is configured to move a sanding member in a sanding direction relative to the joint compound specimen supported in a support fixture. An actuator assembly is configured to drive the sanding member into contacting relationship with the joint compound specimen such that the sanding member exerts a controlled amount of pressure against the joint compound specimen. The force gauge is configured to measure a resistance force against the sanding member in a resistance direction in opposing relationship to the sanding direction. A processor programmed with a joint compound analyzing application is configured to use a force signal from the force gauge that is indicative of the resistance force to determine the sandability value for the joint compound specimen.

Abstract: The invention relates to a method for quantifying emitting particles and for characterizing the time-dependent behavior of the particles. The number n of emissions of the particles in the measuring period that have been detected in a time interval having a predetermined interval width within the measuring period is ascertained, wherein the evaluation is performed particularly for a plurality of time intervals having the same interval width, with a distribution function p(n) for the number n of detected emissions being determined. For the interval width different bin times ? are stipulated, and, for each bin time ?, the evaluation is performed and a distribution function p?(n) is ascertained, wherein, for each bin time ?, moments mi,?Mess for the distribution function p?(n) are ascertained, from which bin time dependent moment functions miMess(?) are presented.

Abstract: An organic light emitting diode display includes a first thin film transistor of which a channel is formed in a polycrystalline transistor, a second thin film transistor of which a channel is formed in an oxide semiconductor layer, an organic light emitting diode electrically connected to the first thin film transistor, a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to a gate electrode of the first thin film transistor, and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is positioned higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

Abstract: Methods, apparatuses, and systems related to reduction of roughness on a sidewall of an opening are described. An example method includes forming a liner material on a first sidewall of an opening in a first silicate material and on a second sidewall of the opening in an overlying second silicate material, where the liner material is formed to a thickness that covers a roughness on the first sidewall extending into the opening. The example method further includes removing the liner material from the first sidewall of the opening and the second sidewall of the opening with a non-selective etch chemistry to reduce the roughness on the first sidewall.

Abstract: A method includes forming an epitaxial source/drain (S/D) feature over a semiconductor layer, where the epitaxial S/D feature includes silicon (Si) and germanium (Ge), forming a trench to expose a portion of the epitaxial S/D feature, annealing the exposed portion of the epitaxial S/D feature, where the annealing forms at a top surface of the epitaxial S/D feature a first region having a first Ge concentration and a second region disposed below the first region having a second Ge concentration that is less than the first Ge concentration, oxidizing the first region, removing the oxidized first region, and forming an S/D contact in the trench over the second region.

Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

Abstract: A current collapse characteristic is sufficiently suppressed. After forming a large opening (first opening) passing through both a TEOS oxide layer 42 and an oxide layer 41, a thin oxide layer (third insulating layer) 43 is formed entirely covering the layers 41 and 42 and the first opening. In the thin oxide layer 43 inside the first opening, a second opening for exposing a group-III nitride semiconductor layer 10 is provided. A gate electrode 50 is formed at a slanted portion of the first opening including the second opening. A taper angle of the first opening is smaller in the TEOS oxide layer 42 than in the oxide layer 41.

Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.

Abstract: A chromatogram data processing system having an impurity detector including a differential chromatogram creator, a purity curve creator and a determiner. The differential chromatogram creator calculates a differential coefficient of an absorbance spectrum with respect to wavelength at a local maximum or local minimum absorption wavelength of the target component, and creates a differential chromatogram which shows a temporal change of the differential coefficient. The purity curve creator creates a purity curve which shows a temporal change of the difference between the degree of similarity of a spectrum on the target peak to a reference spectrum and a threshold of the degree of similarity which is determined taking into account the influence of noise components. The differential chromatogram and the purity curve are displayed on a display unit in a superposed form on a wavelength chromatogram created by a wavelength chromatogram creator.

Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

Abstract: Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.

Abstract: Embodiments of the disclosure relate to systems and methods for monitoring and diagnosing transformer health. In one embodiment, a system incorporating a diagnostic apparatus for monitoring a power transformer can be provided. Various electrical current sensing elements and a dissolved gas analysis (DGA) apparatus are coupled to the transformer and to the diagnostic apparatus. The diagnostic apparatus can be configured to detect a through-fault in the transformer by executing an electrical current flow analysis based at least in part on electrical current values received from the electrical current sensing elements. The electrical current flow analysis involves comparing a ratio of a differential electrical current value and a restraining electrical current value to a threshold value. The diagnostic apparatus can also use DGA data provided by the DGA apparatus to detect an abnormal gas-related condition in the transformer.

Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

Abstract: A semiconductor device includes a well structure having a well dopant, a gate stack structure including first, second, and third stack structures stacked over the well structure, and a channel pattern penetrating the gate stack structure. A sidewall of the gate stack structure is formed with a groove in its sidewall between the first stack structure and the third stack structure such that the first stack structure and the third stack structure protrude farther than the second stack structure in a direction perpendicular to a stacking direction. The channel pattern extends along a surface of a horizontal space between the well structure and the gate stack structure. The semiconductor device further includes a memory pattern extending along an outer wall of the channel pattern, a spacer insulating pattern formed on the sidewall of the gate stack structure, and a doped semiconductor pattern formed on the spacer insulating pattern.

Abstract: A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.

Abstract: An embodiment provides a display device manufacturing method comprising the steps of: preparing a substrate having a plurality of semiconductor chips arranged thereon (S1); bonding at least one first semiconductor chip of the plurality of semiconductor chips to a transfer member (S2); irradiating laser light to the first semiconductor chip to separate the first semiconductor chip from the substrate (S3); disposing the first semiconductor chip on a panel substrate of a display device by means of the transfer member (S4); and irradiating light to the transfer member to separate the first semiconductor chip from the transfer member (S5), wherein the transfer member comprises: a transfer layer and a bonding layer disposed on one surface of the transfer layer; the bonding layer comprises at least one bonding protrusion; and the first semiconductor chip is bonded to the bonding protrusion in step S2.

Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.

Abstract: A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of redistribution lines is on the backside of the device die. The plurality of redistribution lines includes a plurality of metal pads. A polymer layer contacts the plurality of metal pads. A plurality of openings is formed in the polymer layer, with the plurality of metal pads aligned to and exposed to the plurality of openings. The plurality of openings includes a corner opening that is elongated and an additional opening farther away from the corner than the corner opening. The additional opening is non-elongated.