Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Abstract: A nitride power transistor comprises: a silicon substrate comprising a differently doped semiconductor composite structure for forming a space charge depletion region; and a nitride epitaxial layer located on the silicon substrate. With introduction of a differently doped semiconductor composite structure for forming a space charge depletion region inside a silicon substrate of a nitride power transistor, the nitride power transistor is capable of withstanding a relatively high external voltage, and thus a breakdown voltage of the device is improved.

Abstract: An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.

Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.

Abstract: Organic light emitting diode display devices are provided. In at least one embodiment, an organic light emitting diode display device includes a first electrode; a first stack on the first electrode and the first stack is configured to emit a blue colored light; a first charge generating layer on the first stack; a second stack on the first charge generating layer and the second stack is configured to emit a red colored light and a yellow-green colored light; and a second electrode on the second stack. The second stack includes: a red-yellow-green emitting material layer including a yellow-green host, a yellow-green dopant and a red dopant; and a yellow-green emitting material layer including the yellow-green host and the yellow-green dopant.

Abstract: Chemically-sensitive field effect transistors for biosensor chips and system are disclosed. The itransisitors have a multi-layered structure for performing a set of measurements of a biological reaction involving a binding event for one or more biological analytes that may be label-free. The multilayer structure includes a first insulating layer above a substrate layer and a source electrode and a drain electrode disposed positioned over the first insulating layer; a second insulating layer above the first insulating layer and proximate the source and drain electrodes forming side wall members of a well for a fluid comprising the analytes; a 2D graphene layer forming a channel between source and drain electrodes; a solution gate, formed by fluid flowed over the channel, configured to enable determining differences between one or more sample I-Vg curves having a shifted and changed shape relative to a reference curve; embodiments may include ion-selective membranes and/or ion getters.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: A power semiconductor module arrangement includes a substrate including a dielectric insulation layer, a first metallization layer arranged on a first side of the dielectric insulation layer, and a second metallization layer arranged on a second side of the dielectric insulation layer, the dielectric insulation layer being disposed between the first and second metallization layers. The arrangement further includes at least one first connection element mounted on the substrate, a housing having sidewalls, and at least one second connection element. Each second connection element includes a first part extending vertically through a sidewall of the housing, a second part coupled to a first end of the first part and protruding from the sidewall in a vertical direction, and a third part coupled to a second end of the first part opposite the first end. Each third part is detachably coupled to one of the at least one first connection element.

Abstract: An N-type high voltage device includes: a semiconductor layer, a well region, a floating region, a bias region, a body region, a body contact, a gate, a source and a drain. The floating region and the bias region both have P-type conductivity, and both are formed in a drift region in the well region. The bias region is electrically connected with a predetermined bias voltage, and the floating region is electrically floating, to increase a breakdown voltage of the high voltage device and to suppress turning-ON a parasitic transistor in the high voltage device.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: The present invention relates to a method for manufacturing a conductive polymer thin-film having a semiconductor property and to a thin-film transistor including a conductive polymer thin-film having a semiconductor property. The method for manufacturing a conductive polymer thin-film having a semiconductor property includes exposing at least a portion of a conductive polymer thin-film to a surface treatment agent to reduce a charge density of the exposed at least a portion of the conductive polymer thin-film.

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

Abstract: An electrical power distribution system includes a plurality of circuit protection devices coupled between an electrical power source and a plurality of electrical loads. Each circuit protection device includes a trip unit, a network interface communicatively coupled to a communication network including the circuit protection devices, a processor, and a memory. The memory stores instructions that, when executed by the processor, cause the processor to store test operational parameters associated with the circuit protection device, receive a test message including test data representing an electrical condition in the electrical power distribution system, adjust the test operational parameters based on the test data to simulate a response of the trip unit to the electrical condition, generate circuit protection data based on the test data and the adjusted set of test operational parameters, and transmit the circuit protection data to at least one of the communication network and a remote access device.

Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a light-emitting diode (LED) includes a substrate, a carrier confinement (CC) region positioned over the substrate, and an active region position over the CC region. The CC region includes a first CC layer comprising aluminum gallium nitride and a second CC layer position over the first CC layer. The second CC layer also includes aluminum gallium nitride. The active region is configured to have a transient response time of less than 500 picoseconds (ps).

Abstract: Embodiments of a system and a method for evaluating a joint compound specimen can be used to determine a numerical sandability value for the specimen. A moving assembly is configured to move a sanding member in a sanding direction relative to the joint compound specimen supported in a support fixture. An actuator assembly is configured to drive the sanding member into contacting relationship with the joint compound specimen such that the sanding member exerts a controlled amount of pressure against the joint compound specimen. The force gauge is configured to measure a resistance force against the sanding member in a resistance direction in opposing relationship to the sanding direction. A processor programmed with a joint compound analyzing application is configured to use a force signal from the force gauge that is indicative of the resistance force to determine the sandability value for the joint compound specimen.

Abstract: An organic light emitting diode display includes a first thin film transistor of which a channel is formed in a polycrystalline transistor, a second thin film transistor of which a channel is formed in an oxide semiconductor layer, an organic light emitting diode electrically connected to the first thin film transistor, a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to a gate electrode of the first thin film transistor, and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is positioned higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

Abstract: The invention relates to a method for quantifying emitting particles and for characterizing the time-dependent behavior of the particles. The number n of emissions of the particles in the measuring period that have been detected in a time interval having a predetermined interval width within the measuring period is ascertained, wherein the evaluation is performed particularly for a plurality of time intervals having the same interval width, with a distribution function p(n) for the number n of detected emissions being determined. For the interval width different bin times ? are stipulated, and, for each bin time ?, the evaluation is performed and a distribution function p?(n) is ascertained, wherein, for each bin time ?, moments mi,?Mess for the distribution function p?(n) are ascertained, from which bin time dependent moment functions miMess(?) are presented.