Patents Examined by Michele Fan
  • Patent number: 10539968
    Abstract: The disclosed embodiments include a computer implemented method, apparatus, and computer program product that includes executable instructions that when executed performs operations for method for determining flow control device (FCD) properties for both an injection well and a production well in coupled injector-producer liquid flooding systems that yields uniform flooding along the production well.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 21, 2020
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Andrey Filippov, Vitaly Khoriakov
  • Patent number: 10526880
    Abstract: The disclosed embodiments include a computer implemented method, apparatus, and computer program product that includes executable instructions that when executed performs operations for determining flow control device (FCD) properties for an injection well that yields uniform flooding along the production well.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 7, 2020
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Andrey Filippov, Vitaly Khoriakov
  • Patent number: 10527546
    Abstract: Embodiments of the present disclosure describe a method for determining a property of an uncharacterized crude oil sample using a polynomial equation correlating the property to a spectrum index and density of crude oil. The polynomial equation may include constants determined using a data fitting method and a data base of spectral data, density data, and standard properties data of a plurality of crude oils.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 7, 2020
    Assignee: Saudi Arabian Oil Company
    Inventors: Omer Refa Koseoglu, Adnan Al-Hajji, Ezzat Hegazi
  • Patent number: 10529892
    Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 7, 2020
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Japan Science and Technology Agency
    Inventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh K. Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 10520925
    Abstract: The disclosed embodiments include a computer implemented method, apparatus, and computer program product that includes executable instructions that when executed performs operations for method for determining flow control device (FCD) properties for a production well in coupled injector-producer liquid flooding systems that yields a uniform flooding front along the production well.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 31, 2019
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Andrey Filippov, Vitaly Khoriakov
  • Patent number: 10516042
    Abstract: An III group nitride semiconductor device comprises: a substrate; a nitride semiconductor layer located on the substrate; a passivation layer located on the nitride semiconductor layer, a portion of the passivation layer in a gate region being etched to expose the nitride semiconductor layer so as to form a gate groove; a composite dielectric layer located on the passivation layer and the gate groove, the composite dielectric layer comprising one or more combination structures of two or more of a nitride dielectric layer, an oxynitride dielectric layer and an oxide dielectric layer which are formed sequentially in the direction away from the substrate; and a source electrode and a drain electrode respectively located in a source region and a drain region on the nitride semiconductor layer, and a gate electrode located in a gate region between the source region and the drain region on the composite dielectric layer.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 24, 2019
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10502678
    Abstract: Embodiments of the present invention encompass systems and methods for determining detection limits for various antibody-dye conjugates for flow cytometry. Exemplary techniques involve a linear superpositioning approach of spillover-induced enlargements of normally distributed measurement errors.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 10, 2019
    Assignee: Beckman Coulter, Inc.
    Inventor: Michael Kapinsky
  • Patent number: 10494670
    Abstract: Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 3, 2019
    Inventors: Pieter van Rooyen, Mitchell Lerner, Paul Hoffman
  • Patent number: 10497766
    Abstract: A display device and manufacturing method thereof with a high level of reliability is provided without increasing the number of manufacturing processes. The display device includes a first conductor, a first insulation layer including a first contact hole exposing a part of the first conductor, a second insulation layer including a second contact hole exposing at least a part of the first contact hole and a part of a surface of the first insulation layer, a pixel electrode overlapping a part of the second contact hole and electrically connected to the first conductor, and a third insulation layer contacting the first insulation layer via the second contact hole.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 3, 2019
    Assignee: Japan Display Inc.
    Inventors: Kenta Kajiyama, Masakazu Kaida
  • Patent number: 10483359
    Abstract: Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Timothy D. Henson, Kapil Kelkar, Ljubo Radic
  • Patent number: 10475944
    Abstract: A solar cell module is discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and a plurality of first electrodes and a plurality of second electrodes, which are formed on a back surface of the semiconductor substrate and are separated from each other, the plurality of solar cells disposed in a first direction; a plurality of first conductive lines connected to the plurality of first electrodes included in a first solar cell of the plurality of solar cells, and the plurality of first conductive lines extended in the first direction; a plurality of second conductive lines connected to the plurality of second electrodes included in a second solar cell of the plurality of solar cells which is adjacent to the first solar cell, and the plurality of second conductive lines extended in the first direction.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 12, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Bojoong Kim, Minpyo Kim, Daehee Jang, Hyeyoung Yang
  • Patent number: 10475738
    Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Mu-Kai Tsai, Chung-Hsing Lin
  • Patent number: 10466677
    Abstract: The systems and methods disclosed herein include an assessment system and process for assessing an industrial machine and its various sections, sub-sections, and parts. In embodiments, the assessment system includes an assessment device that includes an assessment overviewer and a part assessor. The assessment overviewer provides an assessor with a selectable industrial machine schematic that illustrates the assessment status of each section of the industrial machine, such as by changing the appearance of each section based its assessment status. The part assessor provides a part assessment interface with engineering instructions and a part grading user interface that provides for a comparison of digital images to complete the part grading.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 5, 2019
    Assignee: Solar Turbines Incorporated
    Inventors: Jonathan Bendert, Pier Paolo Piattini, Francesc Diaz Trias, Chandrakanth Reddy Boppidi, Venkatesh Lingineni, Martin Rinak, Karol Sykora, Martin Velgos
  • Patent number: 10466225
    Abstract: A method and a system for detecting a fuel quality in a vehicle including a first determination unit to determine a correction factor kkW for fuel as a quotient between an output fokW required to propel a vehicle and a reference output engkW which an engine in the vehicle is estimated to yield; k k ? ? W = fo k ? ? W eng k ? ? W ; a second determination unit to determine a correction factor kNOx for exhaust gas emissions as a quotient between a value measured in the vehicle for nitrogen oxides engNOx and a reference value for nitrogen oxides ECUNOx; k NOx = eng NOx ECU NOx ; and a detection unit to detect the fuel quality based on a relation between the correction factor kkW for fuel and the correction factor kNOx for exhaust gas emissions.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 5, 2019
    Assignee: SCANIA CV AB
    Inventor: Mikael Nordin
  • Patent number: 10461024
    Abstract: In a semiconductor device, first to fourth circuit patterns are formed on an insulating substrate in a case. A first end of a first lead frame is connected via solder to the first circuit pattern and another end of the first lead frame extends outside from the case. In the same way, a first end of a second lead frame is connected via solder to the fourth circuit pattern and another end extends outside from a case. Portions of the second and third circuit patterns are covered by the first lead frame and are respectively buried by insulating layers. In addition, a semiconductor element is provided via solder on a region of the first lead frame above the first circuit pattern. Wires electrically connect the semiconductor element and a region of the second lead frame above the fourth circuit pattern.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 29, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takashi Katsuki
  • Patent number: 10461123
    Abstract: A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction; one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element; a first reflection electrode adjacent the first end portion of the light emitting element; a second reflection electrode adjacent the second end portion of the light emitting element; a first contact electrode connected to the first reflection electrode and the first end portion of the light emitting element; an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and a second contact electrode on the insulating layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Hyun Kim, Jong Hyuk Kang, Joo Yeol Lee, Hyun Deok Im, Hyun Min Cho
  • Patent number: 10439002
    Abstract: A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Murooka
  • Patent number: 10429342
    Abstract: A chemically-sensitive field effect transistor is disclosed herein. The chemically-sensitive field effect transistor comprises a CMOS structure comprising a conductive source and a conductive drain, a channel and an analyte-sensitive dielectric layer. The channel extends from the conductive source to the conductive drain. The channel is composed of a one-dimensional transistor material or a two-dimensional transistor material. The analyte-sensitive dielectric layer is disposed over the channel. An I-V curve or an I-Vg curve is shifted in response to a chemical reaction occurring on or near the chemically-sensitive field effect transistor.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 1, 2019
    Inventors: Paul Hoffman, Mitchell Lerner, Pieter Van Rooyen
  • Patent number: 10429365
    Abstract: For vector A which expresses an absorption spectrum of a target component, vector F orthogonal to vector A is designated as a filter for extracting an impurity superposed on the target component on a chromatogram. For vector I which expresses a measured spectrum obtained by a chromatographic analysis performed on a sample, the inner product of vectors I and F is defined as an index value u of the amount of impurity. If an impurity is present, a peak-like waveform appears on a graph which shows a temporal change in the index value u for the measured spectrum obtained at each point in time of the measurement. By detecting this waveform, the presence or absence of the impurity can be correctly determined. The direction of vector F may be determined so that, when vector B which expresses a spectrum of the impurity is decomposed into vector Ba parallel to vector A and vector Bo orthogonal to vector A, vector F becomes nearly parallel to vector Bo (i.e. the cosine similarity index is maximized).
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 1, 2019
    Assignee: SHIMADZU CORPORATION
    Inventors: Akira Noda, Yasuhiro Mito
  • Patent number: 10431605
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hyun Park, Jun Ho Song, Jean Ho Song, Jae Hak Lee