Abstract: A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Abstract: An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.

Abstract: A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting recovery of information from the plurality of lines is adjusted according to the transitions detected. Examples of such a signal include one or more signals carried on one or more of the plurality of lines and a timing signal carried on a line separate from the plurality of lines.

Abstract: The precharge circuit includes circuitry for initiating charging of a precharge pulse at a first edge of a first clock-like signal. The precharge circuit also includes circuitry for ending the charging of the precharge pulse after a time period that is longer of a preset delay period and a time period designated by a second edge of the second clock-like signal.

Abstract: A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Abstract: A switched-capacitor sample/hold circuit and method having reduced slew-rate and settling time requirements provides for lower-cost and/or lower-power implementation of sample/hold circuits and/or reduced error due to amplifier characteristics. The switched-capacitor sample/hold circuit incorporates a pair of capacitors that are alternatively and mutually-exclusively switched between an input sample position and an amplifier hold position, providing a dual sampled amplifier output signal that has reduced transitions at each sample interval. An alternative embodiment of the sample/hold circuit incorporates a fully-differential amplifier having a differential input and a differential output. Four capacitors are employed forming two of the dual sampled switched-capacitor circuits, one in each negative feedback path (inverted output to non-inverting input, non-inverted output to inverting input) of the amplifier.

Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

Abstract: Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.

Abstract: A method and system for providing variable edge control of pulse waveforms is provided. A positive edge DAC number is set so that the positive edge time of a first pulse waveform of some amplitude is substantially equal to some initial edge time. Similarly, a second positive edge DAC number associated with a second pulse waveform of different amplitude is set so that the positive edge time of the second pulse waveform also equals the initial edge time. Positive gain and offset factors are then generated so that a third positive edge DAC number associated with any pulse waveform may be calculated so that a desired positive edge time of that waveform is produced. Negative edge DAC numbers may be calculated in a similar manner so that the positive and negative edge times of a pulse waveform may be balanced, or more efficient methods may be used.

Abstract: In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.

Abstract: A motor bridge driver interlace, implemented in an ASIC using cost-efficient CMOS technology, is designed to control four external MOS power transistors in a H-bridge configuration for DC-motor driving to achieve accurate and fast switching. Main components of the interface are a charge pump for generating the control voltage for the high-side N-channel MOS transistors, high-side (HSD) circuits, low-side (LSD) circuits and a complex digital interlace for supplying the control signals in a programmable timing scheme. A “strong” charge pump is used to realize a simple CMOS switch to steer the output to the high-side transistors of said H-bridge. The motor bridge is connected to the battery supply by an additional N-channel MOS transistor to implement a reverse supply protection.

Abstract: Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal.

Abstract: An exemplary reduced-power-consumption network includes a frequency divider coupled through global clock lines to a plurality of double-edge triggered registers. Another exemplary network includes a plurality of individually programmable frequency dividers coupled through local clock lines to a plurality of double-edge triggered registers.

Abstract: A second clock is generated as an intermittent train of pulses by removing some pulses from a first clock having a predetermined period, and is supplied as an internal clock to internal circuits of a semiconductor integrated circuit device. At the same time, a current generating circuit for consuming a power supply current is operated in timed relation to a third clock which comprises a train of pulses to be removed from the first clock.

Abstract: Information concerning a condition of a fuse is stored in a latch circuit and may be corrected. A first signal is supplied to the latch circuit which sets the latch circuit in a first state when the fuse is in a first condition and keeps the latch circuit unchanged when the fuse is in a second condition. While the first signal is being supplied, a second signal is supplied to the latch circuit that keeps the latch circuit in the first state when the fuse is in the first condition and sets the latch circuit in a second state when the fuse is in the second condition.

Abstract: A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

Abstract: A gate driving circuit having: a direct current power source; a driving signal source for outputting signal; a main switch device, having a gate terminal in which the signal outputted from the driving signal source is inputted, for controlling a conduction state between a source terminal and a drain terminal; a load energized when the conduction state between the source and drain terminals becomes a conductive state; a reverse current blocking unit, connected between the driving signal source and the gate terminal; and a regenerative unit, connected between the gate terminal and a high potential side of the power source, which becomes a conductive state when the conduction state between the source and drain terminals is a non-conductive state. A gate-source threshold voltage to obtain the conductive state between the source and drain terminals is set higher than an output voltage of the power source.

Abstract: Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

Abstract: A cascaded charge pump based power supply for use with low voltage dynamic random access memory (DRAM) includes a charge pump and a non-overlapping clock signal generator. The charge pump circuit has two pump cascades coupled in parallel. Each pump cascade includes a plurality of pump stages connected serially between a power supply voltage and an output supply node. Adjacent stages of each cascade are clocked on opposite phases of the system clock signal. The charge pump drives an output supply node on both the rising and falling edge of the system clock signal. A non-overlapping clock signal generator for use with a charge pump has a charge sharing transistor which equalizes the non-overlapping output clock signals through charge sharing during the non-overlap period between subsequent phases of the system clock. The charge pump and capacitors are implemented using p-channel devices and the first stage of each cascade is constructed using thin-oxide devices.

Abstract: A frequency divider having an input frequency divider, an edge counter, and an output generator. The input frequency divider generates an intermediate signal having a frequency of fi from an input signal having a frequency fin, wherein fin=2fi. The edge counter generates a value equal to the number of edges in the intermediate signal that have occurred since a reset signal was generated. The output generator generates an output signal when the edge counter value reaches a value Q and generates the reset signal. In one embodiment, the edge counter includes a positive edge counter that counts the number of positive going transitions in the intermediate signal since the reset signal, a negative edge counter that counts the number of negative going transitions in the intermediate signal, and an adder that generates the sum of the positive and negative count values.