Patents Examined by Mohammed A Bashar
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Patent number: 11348658Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.Type: GrantFiled: June 28, 2021Date of Patent: May 31, 2022Assignee: FADU Inc.Inventors: Hongseok Kim, Sang Hyun Park, Sunggil Hong, Hayoung Lim, EHyun Nam
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Patent number: 11342041Abstract: Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.Type: GrantFiled: August 26, 2020Date of Patent: May 24, 2022Assignee: Micron Technology, Inc.Inventor: Sujeet Ayyapureddi
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Patent number: 11328788Abstract: A memory system is disclosed. The memory system includes a first memory array, an error correction code circuit, and a monitor circuit. The error correction code circuit is configured to receive data from the first memory array to correct, at least one error bit in the received data. The error correction code circuit is further configured to generate an error determination signal. The monitor circuit is coupled to the error correction code circuit. The monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.Type: GrantFiled: September 3, 2020Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Hiroki Noguchi
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Patent number: 11328769Abstract: A resistance change device includes a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer, changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded; a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; and an ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer.Type: GrantFiled: August 6, 2019Date of Patent: May 10, 2022Assignee: FUJITSU LIMITEDInventor: Hideyuki Noshiro
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Patent number: 11315657Abstract: The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.Type: GrantFiled: January 23, 2020Date of Patent: April 26, 2022Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Sungho Kang, Dong Hyun Han, Ha Young Lee
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Patent number: 11309053Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.Type: GrantFiled: September 1, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Takehisa Kurosawa, Koichi Shinohara, Yusuke Tanefusa
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Patent number: 11302367Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.Type: GrantFiled: October 1, 2018Date of Patent: April 12, 2022Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 11302411Abstract: A TPM with programmable fuses in an SOC includes an on-die RAM storing a blown-fuse count and a TPM state read from off-die NV memory. During initialization, if the blown-fuse count is greater than a TPM state fuse count, a TPM state PIN-attempt-failure count is incremented, thereby thwarting a replay attack. If a PIN satisfies a PIN failure policy, and if a TPM state previously-passed-PIN indicator is set to true, a fuse is blown and the blown-fuse count incremented depending on the PIN being incorrect, but if the TPM state previously-passed-PIN indicator is set to false, a fuse is blown and the blown-fuse count incremented independent of whether the PIN is correct or incorrect. The TPM state fuse count is set equal to the blown-fuse count. If a counter cleared before processing the PIN remains cleared during the next initialization, a fuse voltage cut is detected and a penalty imposed.Type: GrantFiled: March 31, 2021Date of Patent: April 12, 2022Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ling Tony Chen, Felix Domke, Ankur Choudhary, Bradley Joseph Litterell
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Patent number: 11289172Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.Type: GrantFiled: February 9, 2021Date of Patent: March 29, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg
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Patent number: 11289159Abstract: A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.Type: GrantFiled: December 19, 2019Date of Patent: March 29, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Florian Longnos, Engin Ipek, Shihai Xiao
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Patent number: 11289486Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.Type: GrantFiled: March 27, 2019Date of Patent: March 29, 2022Assignees: SK hynix Inc., Duality Inc.Inventor: Jin Hong Ahn
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Patent number: 11281401Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).Type: GrantFiled: September 23, 2019Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Peter Mayer, Michael Dieter Richter, Martin Brox, Wolfgang Anton Spirkl, Thomas Hein
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Patent number: 11276477Abstract: A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller.Type: GrantFiled: October 26, 2020Date of Patent: March 15, 2022Assignee: SK HYNIX INC.Inventors: Su Jin Lim, Min Hwan Moon
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Patent number: 11276472Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.Type: GrantFiled: July 22, 2020Date of Patent: March 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Hun Kwak
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Patent number: 11276460Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.Type: GrantFiled: August 30, 2019Date of Patent: March 15, 2022Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Jianxun Sun, Juan Boon Tan, Tu Pei Chen, Eng Huat Toh
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Patent number: 11276453Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.Type: GrantFiled: May 20, 2020Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Christopher E. Cox, Bill Nale
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Patent number: 11270746Abstract: A word line driver circuit is disclosed. A word line driver circuit may include a circuit configured to generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a first control signal triggering an active mode. The circuitry may further be configured to generate an internal global word line voltage based on the clamped voltage during the active mode. Further, the word line driver circuit may include at least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage. Additionally, the word line driver circuit may include at least one sub word line driver configured to receive the global word line voltage and generate a word line voltage.Type: GrantFiled: August 22, 2019Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventor: Tae H. Kim
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Patent number: 11264110Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high P-E cycles, the amplitude of a refresh voltage for a single-level cell (SLC) block can be 0 V or lower while the amplitude of a refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage.Type: GrantFiled: February 13, 2020Date of Patent: March 1, 2022Assignee: SanDisk Technologies LLCInventors: Abhijith Prakash, Jiahui Yuan
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Patent number: 11257553Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.Type: GrantFiled: April 23, 2021Date of Patent: February 22, 2022Assignee: SILICON STORAGE TECHNOLOGY, INC.Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
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Patent number: 11231996Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.Type: GrantFiled: December 30, 2020Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
