Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.

Abstract: A memory device includes a memory bank having multiple addressable groups of memory cells. The multiple addressable groups of memory cells include a primary set of addressable groups and a secondary set of addressable groups. The memory bank has a control circuitry that activates an addressable group with the control circuitry including repair address match circuitry that includes dynamic selection circuitry having multiple first inputs that receive row address values corresponding to the primary set. The dynamic selection circuitry includes one or more second inputs configured to receive one or more fused address values corresponding to the secondary set of addressable groups. The dynamic selection circuitry includes an output configured to selectively transmit a result that is based at least in part on a selection of one or more first inputs and a comparison of the selected one or more first inputs with the one or more the second inputs.

Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.

Abstract: The Zeeman shift of electronic spins in nitrogen-vacancy (NV) centers in diamond has been exploited in lab-scale instruments for ultra-high-resolution, vector-based magnetic sensing. A quantum magnetometer in CMOS utilizing a diamond-nanocrystal layer with NVs or NV-doped bulk diamond on a chip-integrated system provides vector-based magnetic sensing in a compact package. The system performs two functions for the quantum magnetometry: (1) strong generation and efficient delivery of microwave for quantum-state control and (2) optical filtering/detection of spin-dependent fluorescence for quantum-state readout. The microwave delivery can be accomplished with a loop inductor or array of wires integrated into the chip below the nanodiamond layer or diamond. And the wire array can also suppress excitation light using a combination of plasmonic and (optionally) Talbot effects.

Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

Abstract: A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: A system includes a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and a processing device, operatively coupled to the memory device, to: determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold; modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold; and add a new start voltage value to the modified set of start voltage values.

Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

Abstract: Methods, systems and devices for reading data stored in a polymer (e.g., DNA) and for verifying the sequence of a polymer synthesized in situ in a nanopore-based chip, include providing a resonator having an inductor and a cell, the cell having a nanopore and a polymer that can traverse through the nanopore, the resonator having an AC output voltage frequency response at a probe frequency in response to an AC input voltage at the probe frequency, providing the AC input voltage having at least the probe frequency, and monitoring the AC output voltage at least at the probe frequency, the AC output voltage at the probe frequency being indicative of the data stored in the polymer at the time of monitoring, wherein the polymer includes at least two monomers having different properties causing different resonant frequency responses.

Abstract: A majority voting processing device performs majority voting on respective bits of information data piece including r-number of bits (r is an integer of 2 or greater). The device includes a memory including a plurality of memory element groups each including r-number of memory elements that store data for the corresponding r-number of bits, respectively, the plurality of memory element groups each being provide for one address. A memory access unit writes each bit of the information data piece in k-number (k is an odd number of 3 or greater) of the memory elements in the memory element group corresponding to one address, and reads out the k-number of bits written in the k-number of the memory elements corresponding to that one address. A majority voter that performs majority voting on the k-number of bits read out from the memory by the memory access unit.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Abstract: A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.

Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.