Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

Abstract: A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.

Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

Abstract: A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller.

Abstract: Apparatus and methods relating to programmable superconducting cells are described. A programmable superconducting cell can be formed from a superconducting current loop having at least two terminals connected to the loop. The current loop and terminals can be formed from a single layer of superconducting material. The programmable superconducting cell can be incorporated into a crossbar architecture to form a high-speed vector-matrix multiplying processor for deep neural network computations.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.

Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.

Abstract: The invention relates to a DRAM structure which comprise a capacitor set and at least a transistor. The capacitor set includes a first capacitor with a first electrode and a second capacitor with a second electrode, and a counter electrode is shared by the first and the second capacitors. The counter electrode is perpendicular or substantially perpendicular to an extension direction of an active region of the transistor, or the counter electrode is not positioned above or below the first and second electrode.

Abstract: A method is provided for error detection in a ternary content addressable memory, TCAM, preferably in real-time, wherein the error detection is initiated with a read operation at a specified input address (200), wherein an additional random access memory, RAM, is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (210) which each consist of data and a mask are placed at the same address locations. In addition, a method is provided for error detection in a TCAM, preferably in real-time, wherein the error detection is triggered by the found of searched input key (400) and starts with a read operation at a specified memory address (410), wherein an additional RAM is provided, wherein said RAM has the same number of locations as the TCAM, wherein in both memories, TCAM and RAM, corresponding read data entries (420) which each consist of data and a mask are placed at the same address locations.

Abstract: A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.

Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.

Abstract: A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

Abstract: Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

Abstract: The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N?1 of the consecutive read operations, and N is an integer number of the consecutive read operations.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.