Patents Examined by Mohammed A Bashar
  • Patent number: 11450403
    Abstract: Disclosed herein is an apparatus that includes a first address generator generating a first address in response to a clock signal; a second address generator generating a second address corresponding to the first address; a first detection circuit activating a first signal when the second address matches with a third address; a second detection circuit activating a second signal when the second address indicates a predetermined state; a first latch circuit latching the first address in response to the first signal; a second latch circuit latching the first address in response to the second signal; a third detection circuit activating a third signal when the first address matches with an address stored in the first latch circuit; a fourth detection circuit activating a fourth signal when the first address matches with an address stored in the second latch circuit; and a first selector selecting the third or fourth signal.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 11443807
    Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: September 13, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Li Hong Xiao, Zhiliang Xia
  • Patent number: 11430523
    Abstract: A storage device is provided. The storage device includes a nonvolatile memory device including a first block and a second block, and a controller including processing circuitry configured to, predict a number of writes to be performed on the nonvolatile memory device using a machine learning model, determine a type of reclaim command based on the predicted number of writes, the reclaim command for reclaiming data of the first block to the second block, and issue the reclaim command.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Woo Hong, Chan Ha Kim, Yun Jung Lee
  • Patent number: 11423952
    Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 23, 2022
    Assignee: XILINX, INC.
    Inventors: Narendra Kumar Pulipati, Sree RKC Saraswatula, Santosh Yachareni, Shidong Zhou
  • Patent number: 11423985
    Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 23, 2022
    Assignee: Arm Limited
    Inventors: Fernando Garcia Redondo, Shidhartha Das, Glen Arnold Rosendale, George McNeil Lattimore, Mudit Bhargava
  • Patent number: 11417409
    Abstract: An electronic device includes a pattern data generation circuit and a data input/output (I/O) circuit. The pattern data generation circuit generates pattern data having a serial pattern based on a command/address signal. The data I/O circuit outputs the pattern data or read data as internal data based on a read command for a read operation and an internal command in a test mode. The data I/O circuit receives and stores the internal data, which are output, as write data for a write operation.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Seung Kim
  • Patent number: 11417408
    Abstract: A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jongpil Son
  • Patent number: 11404117
    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
  • Patent number: 11398291
    Abstract: A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 26, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Patent number: 11398288
    Abstract: A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 26, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Phil Reusswig, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Patent number: 11398289
    Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 26, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Tanmoy Roy, Anuj Grover
  • Patent number: 11393553
    Abstract: A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 19, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Chuanqi Shi, Heng-Chia Chang, Li Ding
  • Patent number: 11393552
    Abstract: Methods, apparatuses and electronic devices for testing a memory of a chip are provided. Specifically, the chip includes a plurality of operation modules, the operation module includes at least one operation unit, and the operation unit includes at least one memory. The method includes generating a first test vector for a first operation module of the operation modules, and testing the memory in the first operation module by using the generated first test vector independent of other operation modules of plurality of operation modules, where the other operation modules are different from the first operation module.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 19, 2022
    Assignees: Beijing Baidu Netcom Science and Technology Co., Ltd., Kunlunxin Technology (Beijing) Company Limited
    Inventor: Ziyu Guo
  • Patent number: 11393526
    Abstract: Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Abhishek A. Sharma, Prashant Majhi, Brian S. Doyle
  • Patent number: 11380413
    Abstract: The present disclosure provides a test system and a test method. The test system includes: a signal providing module, configured to provide a first clock signal and a second clock signal for a to-be-tested memory, the to-be-tested memory executes a write command based on the first clock signal, so that the to-be-tested memory stores preset data, and the to-be-tested memory executes a read command based on the second clock signal, to read storage data stored in the to-be-tested memory; and one of the first clock signal and the second clock signal is a symmetrical clock signal, and the other is an asymmetrical clock signal with a preset duty cycle; and a processing module, configured to obtain the storage data, and obtain a clock signal tolerance of the to-be-tested memory according to a comparison result between the storage data and the preset data.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: July 5, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YiFei Pan
  • Patent number: 11380415
    Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Patent number: 11367496
    Abstract: The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 21, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki Tezuka, Masami Kuroda
  • Patent number: 11355214
    Abstract: Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Junam Kim
  • Patent number: 11348655
    Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11347403
    Abstract: Technologies are described herein for or extending the lifespan of a solid-state drive by using worn-out MLC flash blocks in SLC mode to extend their useful life. Upon identifying a first storage location in the storage media of an SSD as a candidate for defecting, the first storage location is switched from a first programming mode to a second programming mode, where the second programming mode results in a lower storage density of storage locations than the first programming mode. In conjunction with switching the first storage location to the first programming mode, a second storage location in the storage media is switched from the second programming mode to the first programming mode to ensure that the total capacity of the storage media remains at or above the rated capacity.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 31, 2022
    Assignee: Seagate Technolagy LLC
    Inventors: Darshana H. Mehta, Antoine Khoueir