Patents Examined by Mohammed A Bashar
  • Multi-state programming in memory device with loop-dependent bit line voltage during verify
    Patent number: 10706941
    Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
  • Semiconductor memory devices, memory systems including the same and methods of operating memory systems
    Patent number: 10705908
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Read threshold voltage selection
    Patent number: 10706897
    Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chandra C. Varanasi
  • Memory controller for controlling memory device based on erase state information and method of operating the memory controller
    Patent number: 10706944
    Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jeong So, Dong-Hwan Lee, Seong-Hyeog Choi, Eun-Chu Oh, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon
  • Periodic calibrations during memory device self refresh
    Patent number: 10692560
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Bill Nale
  • Semiconductor memory device, memory system, and refresh method thereof
    Patent number: 10692561
    Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-soo Jang, Eunsung Seo, Seungjun Bae
  • Strapping structure of memory circuit
    Patent number: 10685952
    Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Voltage control circuit including assist circuit and memory device including the same
    Patent number: 10672442
    Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-yeop Baeck, Siddharth Gupta, In-hak Lee, Jae-seung Choi, Tae-hyung Kim, Dae-young Moon, Dong-wook Seo
  • Nonvolatile digital computing with ferroelectric FET
    Patent number: 10672475
    Abstract: Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS?VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 2, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma
  • Non-volatile memory device and operating method thereof
    Patent number: 10665302
    Abstract: An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 26, 2020
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Bong-Soon Lim, Sang-Hyun Joo, Kee-Ho Jung
  • Memory device with discharge voltage pulse to reduce injection type of program disturb
    Patent number: 10665306
    Abstract: Techniques are disclosed for reducing an injection type of program disturb in a memory device. In one aspect, a discharge operation is performed at the start of a program loop. This operation discharges residue electrons from the channel region on the source side of the selected word line, WLn, to the channel region on the drain side of WLn. As a result, in a subsequent channel pre-charge operation, the residue electrons can be more easily removed from the channel. The discharge operation involves applying a voltage pulse to WLn and a first set of drain-side word lines which is adjacent to WLn. The remaining unselected word lines may be held at ground during the voltage pulse.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 26, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Henry Chin
  • Semiconductor device
    Patent number: 10665276
    Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Suk Seo
  • Memory system and method for controlling memory system
    Patent number: 10658055
    Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Semiconductor devices
    Patent number: 10658015
    Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Min Su Park, Sun Myung Choi
  • Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor
    Patent number: 10658033
    Abstract: A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: May 19, 2020
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Sung Hyun Jo
  • Vertical resistive processing unit with air gap
    Patent number: 10658582
    Abstract: A vertical resistive unit is provided. The vertical resistive unit includes first and second resistive random access memory (ReRAM) cells. The first ReRAM cell includes first vertically aligned horizontal electrode layers and first vertical electrodes operably extending through the first vertically aligned horizontal electrode layers. The second ReRAM cell includes second vertically aligned horizontal electrode layers and second vertical electrodes operably extending through the second vertically aligned horizontal electrode layers. The first and second ReRAM cells are disposed to define an air gap between the first and second ReRAM cells.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Systems and methods for writing, reading, and controlling data stored in a polymer
    Patent number: 10640822
    Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive or impedance variance, e.g., via a change in a resonant frequency response, as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 5, 2020
    Assignee: IRIDIA, INC.
    Inventors: Paul F. Predki, Maja Cassidy
  • Non-volatile memory with countermeasure for program disturb including purge during precharge
    Patent number: 10643718
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • Method for overlapping memory accesses
    Patent number: 10635357
    Abstract: Improved methods and systems for accessing a memory in a computer are disclosed. In one embodiment, the true and complement portions of a differential write clock signal are employed as two single ended clock signals for independently controlling different memory chips in a memory system. For example, in a memory system having two memory chips, one memory chip is configured to use the true write clock signal and the other memory chip is configured to use the complement write clock signal. Employing the differential write clock signal as two single ended clock signals allows overlapping of write and read operations across multiple memory chips, reducing the time needed for accessing memory. Accordingly, the disclosed methods and systems provide a more efficient memory system that can be used to improve the operation of a computer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 28, 2020
    Assignee: Nvidia Corporation
    Inventor: Michael Halfen
  • Memory system and operating method thereof
    Patent number: 10628067
    Abstract: A memory system includes: a plurality of nonvolatile memory devices each including a plurality of memory blocks; and a controller configured to select an innocent open super block among super blocks formed across the nonvolatile memory devices when determining that sequential write operations are to be performed, and perform the sequential write operations on the innocent open super block.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park