Abstract: A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.

Abstract: A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

Abstract: Methods, systems, and devices for enabling fast pulse operation are described. A threshold voltage of a selection component and a requisite duration for a voltage applied to a selection component to reach a threshold voltage in response to a voltage generated by an external source may be determined. The threshold voltage may correspond to a voltage at which the selection component is configured to release electric charge. A voltage may then be generated and applied to an access line that is in electronic communication with the selection component and a memory cell for at least the requisite duration. Electric charge may be stored at the selection component during the requisite duration and transferred to memory cell after the requisite duration.

Abstract: Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing the cells to one state while a sense component is isolated from digit lines of the array. Read or write operations may be executed at the sense component while the sense component is isolated, and the cell may be de-isolated (e.g., connected to the digit lines) when write operations are completed. The techniques may include techniques accessing a memory cell of a memory array, isolating a sense amplifier from a digit line of the memory array based at least in part on the accessing of the cell, firing the sense amplifier, and pre-writing the memory cell of the memory array to a second data state while the sense amplifier is isolated. In some examples, the memory cell may include a ferroelectric memory cell.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.

Abstract: Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

Abstract: The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N?1 of the consecutive read operations, and N is an integer number of the consecutive read operations.

Abstract: The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.

Abstract: A semiconductor memory device includes a word line connected to memory cells, bit lines respectively connected to the memory cells, and a control circuit configured to control voltages applied to the word line and the bit lines during a write operation. When writing data into a target memory cell, the control circuit executes first and second loops in sequence. In executing the first loop, the control circuit applies a first program voltage to the word line during the program operation, and applies a verify voltage to the word line during the verify operation, and upon detecting that the verify operation neither passed nor failed, the control circuit selects one of two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a sequential position of the first loop in the sequence of loops.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) includes a first memory element configured to perform memory transactions for first memory locations associated with the first memory element via a first memory channel of the dual-channel DIMM, and a second memory element configured to perform memory transactions for second memory locations associated with the second memory element via a second memory channel of the dual-channel DIMM, wherein the first memory channel is different than the second memory channel, and wherein the first memory element is a different type of memory element than the second memory element.

Abstract: A memory system includes: a memory device including a plurality of memory blocks; a memory; a data classifier suitable for classifying check-pointing information stored in the memory as selective information and mandatory information; and a check-pointing component suitable for performing a control to periodically perform a check-pointing operation of programming the selective information and the mandatory information in a memory block, wherein the check-pointing component performs the check-pointing operation by performing a control to program the mandatory information after programming the selective information.

Abstract: A device, for example a memory system, is disclosed wherein two or more operational modes may be set. The clock toggle rate and ODT resistors are dynamically controlled based on one or more of a desired margin of signal integrity, performance, cooling rate, and power consumption.

Abstract: Apparatuses and techniques for compensating for noise, such as a leakage current, in a memory array are described. Leakage currents may, for example, be introduced onto a digit line from unselected memory cells. In some cases, a compensation component may be coupled with the digit line during a first phase of a read operation, before the target memory cell has been coupled with the digit line. The compensation component may sample a current on the digit line and store a representation of the sampled current. During a second phase of the read operation, the target memory cell may be coupled with the digit line. During the second phase, the compensation component may compensate for leakage or other parasitic effects by outputting a current on the digit line during the read operation based on the stored representation of the sampled current.

Abstract: A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: Briefly, embodiments of claimed subject matter relate to circuits and methods for providing signals, such as signals to bring about writing of binary logic values to magnetic random-access memory (MRAM) cells. In particular embodiments, such circuits may operate to control output signal variability over an operating temperature range.

Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating and using such structures. Non-volatile memory elements are arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal. A first field-effect transistor is coupled with the first terminal of the Wheatstone bridge arrangement, and a second field-effect transistor is coupled with the second terminal of the Wheatstone bridge arrangement.

Abstract: A motherboard is provided. The motherboard includes a memory module, a processor and a memory slot. The memory module includes a first memory rank, a second memory rank, a plurality of first pins coupled to the first memory rank and a plurality of second pins coupled to the second memory rank. The processor includes a memory channel. The memory slot is coupled between the processor and the memory module, and is configured to transmit a first control signal from the memory channel to at least one of the plurality of first pins, or transmit a second control signal from the memory channel to at least one of the plurality of second pins. The first memory rank receives the first control signal through at least one of the plurality of first pins. The second memory rank receives the second control signal through at least one of the plurality of second pins.

Abstract: A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.

Abstract: A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.