Patents Examined by Mohammed A Bashar
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Patent number: 11651201Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.Type: GrantFiled: July 26, 2019Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Kyung Kim, Soon-Young Kim, Jin-Min Kim, Jae-Hong Min, Sang-Kil Lee, Young-Nam Hwang
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Patent number: 11651834Abstract: A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: updating a setting of the memory device, wherein the setting changes a duty cycle of a signal of the memory device and comprises a first value for a first configuration and comprises a second value for a second configuration; storing error data that indicates errors when using the first configuration and errors when using the second configuration; determining a value for the setting based on the error data, wherein the determined value minimizes errors associated with the memory device; and storing the determined value for the setting of the memory device.Type: GrantFiled: May 11, 2021Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Yang Lu, Zhenming Zhou, Jiangli Zhu, Tingjun Xie
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Patent number: 11646091Abstract: A system for outputting test data from cores to one communication interface. The system includes shared memories corresponding to the cores. Each shared memory includes a ring buffer and an array of slots. Each core generates a diagnostic message, and stores the generated diagnostic message in a select memory region of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among diagnostic messages stored in the shared memories, and outputs the first diagnostic message to a personal computer through the communication interface.Type: GrantFiled: September 22, 2021Date of Patent: May 9, 2023Assignee: SK hynix Inc.Inventor: Siarhei Rusakovich
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Patent number: 11636908Abstract: A memory device to calibrate voltages used to read a group of memory cells. For example, the memory device measures first signal and noise characteristics of a group of memory cells by reading the group of memory cells at first test voltages that are separated from each other by a first voltage interval. An estimate of a read level of the group of memory cells is determined based on the first signal and noise characteristics. The memory device then measures second signal and noise characteristics of the group of memory cells by reading the group of memory cells at second test voltages that are separated from each other by a second voltage interval that is smaller than the first voltage interval. An optimized read voltage for the read level is computed from the second signal and noise characteristics.Type: GrantFiled: September 24, 2021Date of Patent: April 25, 2023Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Walter Di Francesco, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey Scott McNeil, Jr.
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Patent number: 11631474Abstract: A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.Type: GrantFiled: October 22, 2021Date of Patent: April 18, 2023Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITYInventors: Sung Ho Kang, Tae Hyun Kim
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Patent number: 11631472Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.Type: GrantFiled: December 17, 2020Date of Patent: April 18, 2023Assignee: Texas Instruments IncorporatedInventors: Devanathan Varadarajan, Varun Singh
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Patent number: 11631449Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.Type: GrantFiled: April 19, 2019Date of Patent: April 18, 2023Inventors: Uksong Kang, Hoiju Chung
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Patent number: 11630993Abstract: An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.Type: GrantFiled: December 4, 2019Date of Patent: April 18, 2023Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: François Rummens, Alexandre Valentian
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Patent number: 11621047Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.Type: GrantFiled: July 30, 2021Date of Patent: April 4, 2023Assignee: SK hynix Inc.Inventors: Jeong Jun Lee, Soo Hwan Kim, Mi Hyun Hwang
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Patent number: 11600310Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.Type: GrantFiled: February 7, 2022Date of Patent: March 7, 2023Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 11600356Abstract: The disclosure provides a memory device which includes a plurality of word lines grouped into a plurality of WL sets; and a plurality of redundant word lines grouped into M RWL sets; and a memory control circuit connected to the WL sets and the RWL sets and configured to replace a plurality of defective WL sets of the plurality WL sets by selecting from the RWL sets, wherein each of the plurality of defective WL sets comprises at least a defective word line, all of the M RWL sets are available for repairing the WL sets during a wafer stage, where M is an integer greater than 2, and N of M RWL sets is available for repairing the WL sets during the wafer stage, during a package stage and during a post package stage, where N is an integer less than M.Type: GrantFiled: September 16, 2021Date of Patent: March 7, 2023Assignee: Winbond Electronics Corp.Inventors: Kan-Yuan Cheng, Hee-Seong Kim, Sangho Shin, Tien-Chieh Huang
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Patent number: 11594286Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.Type: GrantFiled: February 4, 2022Date of Patent: February 28, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Hun Kwak
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Patent number: 11593199Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.Type: GrantFiled: December 27, 2021Date of Patent: February 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
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Patent number: 11587633Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.Type: GrantFiled: June 16, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Taeksang Song, Hyunyoo Lee, Saira Samar Malik, Kang-Yong Kim
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Patent number: 11581055Abstract: A memory system includes a memory device and a controller. The controller is coupled to the memory device through input/output (I/O) lines. The controller includes an interface component and a dummy power consumption component. The interface component performs a signal training operation for adjusting a timing of a clock signal, to which test data is synchronized. The dummy power consumption component performs a dummy power consumption operation while the signal training operation is performed.Type: GrantFiled: August 3, 2021Date of Patent: February 14, 2023Assignee: SK hynix Inc.Inventors: Hyun Sub Kim, Ie Ryung Park
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Patent number: 11567695Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.Type: GrantFiled: January 13, 2022Date of Patent: January 31, 2023Assignee: Rambus Inc.Inventor: Scott C. Best
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Patent number: 11557368Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.Type: GrantFiled: July 8, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventor: Mohammed Ebrahim H. Hargan
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Patent number: 11557363Abstract: An integrated circuit includes a test counting circuit, a test information storage circuit, a sequence control circuit and a driving circuit. The test counting circuit generates a counting address signal. The test information storage circuit stores a test control value and outputs the test control value based on the counting address signal. The sequence control circuit changes an output sequence of the test control value based on a sequence control signal and outputs a final test control value based on the test control value or a target control value. The driving circuit performs a pre-set test operation based on the final test control value.Type: GrantFiled: January 15, 2021Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventor: Seung Hyun Chung
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Patent number: 11557362Abstract: A corresponding value of a data state metric associated with each of a value of a plurality of values of a memory access operation parameter used in one or more memory access operation is measured. An optimal metric value based on the measured values of the predetermined data state metric is determined. An optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter is selected.Type: GrantFiled: April 27, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Seungjune Jeon, Tingjun Xie
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Patent number: 11549140Abstract: The disclosure provides a novel system of storing information using a charged polymer, e.g., DNA, the monomers of which correspond to a machine-readable code, e.g., a binary code, and which can be synthesized and/or read using a novel nanochip device comprising nanopores; novel methods and devices for synthesizing oligonucleotides in a nanochip format; novel methods for synthesizing DNA in the 3? to 5? direction using topoisomerase; novel methods and devices for reading the sequence of a charged polymer, e.g., DNA, by measuring capacitive or impedance variance, e.g., via a change in a resonant frequency response, as the polymer passes through the nanopore; and further provides compounds, compositions, methods and devices useful therein.Type: GrantFiled: May 2, 2019Date of Patent: January 10, 2023Assignee: IRIDIA, INC.Inventors: Paul F. Predki, Maja Cassidy