Abstract: A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one current cell will have to be moved in order to place the ECO cell in the target region. Timing slacks for current cells in a neighborhood of the target region are determined. Based on the timing slacks of the current cells, at least one of the current cells is moved to a different location to create sufficient open space to place the ECO cell within the target region.

Abstract: A power supply is disclosed for an industrial control system or any system including a distributed power supply network. In embodiments, the power supply comprises: a battery module including a battery cell and a battery monitor configured to monitor the battery cell; and a self-hosted server operatively coupled with the battery module, the self-hosted server being configured to receive diagnostic information from the battery monitor and provide network access to the diagnostic information. In implementations, the diagnostics stored by the self-hosted server can be broadcast to or remotely accessed by enterprise control/monitoring systems, application control/monitoring systems, or other remote systems via a secured network (e.g., secured access cloud computing environment).

Abstract: An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS) is provided, which mainly has the following contributions. The optimized reconfiguration algorithm based on DVFS proposes a DVFS-based reconfiguration method, which schedules user tasks according to a degree of parallelism (DOP) of the user tasks so as to reconfigure more parallel user tasks, thereby achieving higher reliability. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based heuristic approximation algorithm, which minimizes the delay of the DVFS-based reconfiguration scheduling algorithm. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based method, which reduces memory overhead caused by DVFS-based reconfiguration scheduling. The optimized reconfiguration algorithm based on DVFS improves the reliability of a field programmable gate array (FPGA) system and minimizes the area overhead of a hardware circuit.

Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions.

Abstract: A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.

Abstract: Formal verification methods are used to solve a valid model of a design-under-test (DUT) to enumerate valid coverage points based on an architectural specification of the DUT. A formal solver can be queried to solve for valid solutions by crossing one or more fields of a variable. After each valid solve, values of the variable fields can be recorded and a count for number of valid solutions can be incremented. A new rule can be added to the solving process after each valid solve to invalidate the recorded values of the variable fields for subsequent solves. The count for the number of valid solutions can provide a running total of the valid solutions found for the query. Results of the query can be processed to convert the recorded values to provide the enumerated coverage points. The enumerated coverage points can be converted to test cases for running simulations on the DUT.

Abstract: Provided is a method of controlling a battery pack, and a battery pack controlled by the method. A battery pack includes a plurality of slave battery modules, each of the slave battery modules including a battery that includes at least one battery cell and a slave controller that is configured to control charge and discharge of the battery, a master battery module including a master controller that is configured to control the slave controller, and a communication cable having formed thereon a first port to which the master controller is connected and a plurality of second ports to which the slave controller is connected. The first port includes an identification terminal configured to output an identification signal which is an electrical signal corresponding to the number of the second ports. A method of controlling the battery pack is provided.

Abstract: An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Abstract: Disclosed is an electronic device. The electronic device may include a plurality of interfaces each of which is connected to one peripheral electronic device in a wired manner to deliver power to the connected peripheral electronic device, a power supply circuit connected to the plurality of interfaces, and a control circuit including a plurality of pins each connected to one interface to allow the power supply circuit to supply power to the plurality of interfaces. In addition, various embodiments understood from the disclosure are possible.

Abstract: The present disclosure relates to a system and method for assertion-based formal verification in an electronic design environment. Embodiments may include executing, using a processor, an assertion-based formal verification proof process on a model of an electronic design and analyzing a first property associated with the model. Embodiments may further include generating at least one trace of the first property and determining a mapping function associated with the first property. Embodiments may also include storing the at least one trace and the mapping function. Embodiments may further include determining that a second property associated with the model shares a cone of influence with the first property and generating a new trace based upon, at least in part, the mapping function.

Abstract: A power supply system includes a plurality of sweep modules, a defect detecting unit, and a control unit. Each sweep module includes a battery module and a power circuit module. The defect detecting unit detects a defect for each sweep module. The number of sweep modules is greater S (S?2) than a minimum number of sweep modules required for operation. When the number of defective sweep modules in which a defect has been detected is equal to or less than F (2?F?S), the control unit is configured to disconnect the defective sweep modules from a main line and to continuously execute sweep control.

Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.

Abstract: Disclosed are embodiments to provide a multi-battery energy storage device. One embodiment comprises a first battery and a second battery, with a first circuit branch coupling a positive side of the first battery to a positive side of the second battery, a second circuit branch coupling a positive side of the first battery to a negative side of the second battery, a third circuit branch coupling the negative side of the first battery to the negative side of the second battery, and multiple switchable devices configured to control flow of current through corresponding branches. Other embodiments comprise other configurations and operations.

Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.

Abstract: The invention relates to systems and methods for charging a vehicle. A vehicle and charging station can be designed such that an electric or hybrid vehicle can operate in a fashion similar to a conventional vehicle by being opportunity charged throughout a known route.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.

Abstract: A computer-implemented method and an electronic device for detecting, in an electrical circuit with electrical components (Mg) subject to variations (?) of their model parameters (xj), those components (Mg*) the model parameter variations (?) of which have the strongest influence on a performance (yn) of the circuit, comprising: providing a topology (Q) of the circuit and the model parameters (xj) of all components (Mg) therein; determining, therefrom, topological patterns (Pk) of interconnected components (Mg); generating variation samples (vn), each comprising a different set of candidate variations (x?j) of the model parameters (xj); calculating, for each variation sample (vn), the circuit's performance (yn) and a deviation from a standard performance and forming a deviation vector (yD) therefrom; and using the variation samples (vn), the deviation vector (yD) and the topological patterns (Pk) in a regression model for detecting the most influential components (Mg*).

Abstract: Systems and methods for a flexible, head-mounted display is provided. The head-mounted display system may comprise a base member and one or more arm members that are coupled to the base member. Each of the arm members are coupled to the base member via a hinge that allows the arm members to move with respect to one another. Interior walls of the arm members and base member may define one or more chambers. One or more first batteries are positioned within a chamber in the first arm member and one or more second batteries are positioned within a chamber in the second arm member. One or more wired connections coupled to the batteries extend through the arm member(s) and hinges, and into one or more chambers in the base member, where the one or more wired connections are coupled to a battery monitor.