Abstract: A power tool includes a receiving device having at least one first and second power consumption element. A power supply unit connectable to the power tool includes a connecting device having at least one first and second power output element, the receiving device being designed to receive and hold the connecting device, so that the power consumption elements and the power output elements are connectable. Both the first and second power consumption elements have a positive pole as well as a negative pole, and both the first and second power output elements have a positive pole as well as a negative pole. The positive pole of the first power consumption element and the positive pole of the second power consumption element as well as the negative pole of the first power consumption element and the negative pole of the second power consumption element are positioned at a distance from each other in at least one first and second direction.

Abstract: A status signal output circuit outputs a first status signal indicating with a binary level whether or not power the storage unit is normal in accordance with a determination result of the status determination circuit, and, as a second status signal, a pulse width modulation (PWM) signal according to the status of the power storage unit when a measurement circuit including the status determination circuit is normal, or a signal having a axed level when the measurement circuit including the status determination circuit is abnormal. A control signal output circuit outputs, to a drive circuit, a control signal for control to bring a switch inserted between the power storage unit and a load into an OFF state when the power storage unit has abnormality, in accordance with the first status signal and the second status signal output from the status signal output circuit.

Abstract: A communication apparatus (1), such as a mobile phone, a tablet computer or a laptop computer, provides charging reminders to the user of a connected peripheral device (14), such as a headset. The charging reminders are provided in dependence on an auxiliary status signal (AS) received from the peripheral device (14) and on detected charging events (ME), wherein a main charging event (ME) comprises a charging or replacement of a main battery (2) that energizes the communication apparatus (1). The auxiliary status signal (AS) indicates an auxiliary energy level (AL) of an auxiliary battery (15) of the peripheral device (14). The communication apparatus (1) detects low-battery conditions (LC), based on the indicated auxiliary energy level (AL), and provides notification signals (NS) for a user interface (11) to notify the user of the detected low-battery conditions (LC) in response to the detected main charging events (ME).

Abstract: The present disclosure provides a battery protection board, including: a body; a voltage jump detection circuit, disposed on the body, and configured to detect whether a voltage jump occurs in a voltage of a battery, and to output a voltage jump signal when a voltage jump occurs in the voltage of the battery; and a battery protection unit, coupled to an output end of the voltage jump detection circuit, and configured to determine that the battery is damaged when the voltage jump signal is received, and to protect the battery. The present disclosure also discloses a battery assembly having the above battery protection board and a terminal device having the battery assembly.

Abstract: A vehicle includes an electric machine, a battery, and a controller. The electric machine is configured to deliver power to wheels to drive the vehicle. The battery has an array of cells that are configured to deliver electrical power to the electric machine. The controller is programmed to, in response to a charge imbalance within the array of cells, simultaneously discharge a number of cells within the array based on a temperature of the controller.

Abstract: Embodiments discussed herein refer to backwards compatible charging circuits and methods for charging a battery to a relatively high voltage level regardless of whether the charging station is capable of supplying power at that relatively high voltage level. The circuitry and methods according to embodiments discussed herein can use the onboard charging system to provide a voltage boosting path to increase the charge voltage from a legacy voltage level (e.g., a relatively low voltage level) to a native voltage level (e.g., a relatively high voltage level). When a native voltage charging station is charging the battery, the circuitry and methods according to embodiments discussed herein can use a native voltage path for supplying power, received from the charging station at the native voltage, to the battery.

Abstract: Provided are a communication system of a battery pack, and a battery pack including the communication system.

Abstract: An approach is described for enhancing the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration. The technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The analog satisfiability (aSAT) methodology is applied to parameter biasing obfuscation, where the width of a transistor is obfuscated to mask circuit properties, while also limiting the number of keys that produce the target performance requirements.

Abstract: A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: An electrical apparatus incorporates a first rechargeable battery (11) and a second rechargeable battery (12) connected in parallel with the first rechargeable battery (11), the second rechargeable battery (12) having an allowable maximum discharge current larger than that of the first rechargeable battery (11). The electrical apparatus includes: a power supply path (15a) configured to input power supplied from the first rechargeable battery (11) and from the second rechargeable battery (12) to a load (15); and a discharge current limiting circuit connected serially with the first rechargeable battery (11) and configured to perform control in such a manner that a discharge current flowing from the first rechargeable battery (11) to the second rechargeable battery (12) and/or to the power supply path (15a) does not exceed the maximum discharge current of the first rechargeable battery (11).

Abstract: A voltage equalizer includes: first, second, and third junction terminals respectively connected to a positive electrode of a first battery module, a positive electrode of a second battery module, and negative electrodes of the first and second battery modules; an equalizer circuit connected between the first and second junction terminals, and the equalizer forming a current path between the first and second junction terminals; a first indicator having a first displaying state that changes according to a voltage difference between the first and second junction terminals; a first comparator for outputting a first output voltage according to an input voltage that is input in proportion to a voltage between the first and third junction terminals; and a second indicator having a second displaying state that changes according to the first output voltage of the first comparator.

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.

Abstract: A battery module including a plurality of battery cells and a cell balancing system having a respective battery cell monitoring module attached to each battery cell and a module carrier having second connection means for connection of a positive terminal of the battery cell to a negative terminal of an adjacent battery cell and for an electrical connection of a negative terminal of the battery cell to a positive terminal of another adjacent battery cell. The battery cell monitoring modules are connected to one another by a balancing bus for transmitting data and electrical current. The electronic battery cell monitoring modules are connected to the positive and negative terminals of the battery cell. The module carrier has two electrical lines and an energy storage module for storing electrical energy. The energy storage module is connected to the two electrical lines to take up or output electrical energy over them.

Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: Program procedures executed to rout a bus, via a processing unit, include a bus information extractor configured to extract bus information including physical requirements for the bus, from input data, a buffer array generator configured to generate a buffer array in which buffers included in the bus are regularly arranged based on the bus information, a buffer array placer configured to place at least one buffer array in the layout of the integrated circuit based on the bus information, and a wiring procedure configured to generate interconnections connected to buffers included in the at least one buffer array based on the bus information.

Abstract: In a method of designing a semiconductor device, a first sub-block included in the semiconductor device is designed by a first EDA tool. A second sub-block included in the semiconductor device is designed by a second EDA tool different from the first EDA tool. A first sub-block model corresponding to the first sub-block and a second sub-block model corresponding to the second sub-block are generated by transforming logical information and physical information associated with one of a result of designing the first sub-block or a result of designing the second sub-block. The first and the second sub-block model have a same format. An integrated physical design for the semiconductor device is obtained by combining the first and the second sub-block based on the first and the second sub-block model. The first and the second EDA tool are configured to design different physical structures for a same logical block.

Abstract: Systems and methods for managing and utilizing heat associated with battery charge and/or discharge cycles are described herein. A system as described herein includes a battery array comprising one or more batteries, a heat collector physically coupled to respective batteries of the battery array that captures heat associated with at least one of charge cycles or discharge cycles of the respective batteries of the battery array, and a routing controller communicatively coupled to the heat collector that initiates transference of the heat captured by the heat collector as an energy source to one or more subsystems that are distinct from the heat collector.

Abstract: Time domain battery usage data of a battery of an electrified powertrain of a vehicle in terms of average SOC, DOD and a set including average current flow rate and average battery temperature for each charge-discharge full cycle and half cycle of the battery during a use period are used to identify a location in a 3-D storage matrix (of fixed size and predetermined discretization levels for each dimension) in memory of an electronic control unit and a count in that location incremented. In an aspect, the charge-discharge full cycles and half cycles are identified using four-point rainflow cycle counting.