Abstract: First and second metrology data are used to train a machine-learning model to predict metrology data for a metrology target based on metrology data for a device area. The first metrology data are for a plurality of instances of a device area on semiconductor die fabricated using a fabrication process. The second metrology data are for a plurality of instances of a metrology target that contains structures distinct from structures in the device area. Using the trained machine-learning model, fourth metrology data are predicted for the metrology target based on third metrology data for an instance of the device area. Using a recipe for the metrology target, one or more parameters of the metrology target are determined based on the fourth metrology data. The fabrication process is monitored and controlled based at least in part on the one or more parameters.

Abstract: A method of designing a semiconductor chip includes: acquiring first data including information about arrangement of a plurality of cells on the semiconductor chip; acquiring second data including information about routing between the plurality of cells and power and signal lines; and outputting a verification result by detecting an error of arrangement of the plurality of cells based on matching of the first data and the second data.

Abstract: Systems and methods that may be implemented to automatically sense and verify proper mated orientation of a removable BGA package relative to a mating pad array (e.g., of a BGA socket) prior to supplying power to the BGA package. A removable BGA package may be provided with first and second symmetric pins so as to present different respective circuit states on opposing sides of a center point of its BGA package pin array, such that proper orientation of the BGA package occurs only when a designated one of the first and second symmetric pins is mated with a designated pad of the mating pad array. A programmable integrated circuit may in turn sense the circuit state presented at the designated pad to verify proper orientation of the mated BGA package based on the sensed circuit state presented at the designated pad, and may take one or more designated actions based on whether or not proper orientation of the mated BGA package is verified.

Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: A logic simulation verification system designates a change timing designation unit configured to designate a reference signal and a change timing and calculate a first time for which there is a possibility that a first signal to be assigned to a variable described in a library, a circuit description, and a test bench is changed in accordance with the reference signal. The system calculates a second time for which there is a possibility that a second signal assigned a variable described in the library, the circuit description, and the test bench will be checked in accordance the reference signal and then determines whether different circuits for which first signals are the same have first times that match. The system also determines whether a first time and a second time match with each other when a first signal of one circuit and a second signal of another circuit are the same.

Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.

Abstract: Disclosed herein are battery management systems and methods for activating battery override logic for a battery management system to provide a power path to a battery pack. A method of activating battery override logic for a battery management system may comprise detecting a predetermined key toggle sequence performed in a predetermined amount of time or detecting an override message received from a CAN bus. The method may further comprise determining if the last override turn-on sequence was requested more than a predetermined amount of time ago, confirming that the override is configured for the contactor, and turning on the contactor to provide a power path to the battery pack for a limited predetermined amount of time. An exemplary predetermined toggle sequence may comprise on-off-on-off-on performed within 10 seconds. An exemplary override message from the CAN bus may be initiated by a user having a key, code, or access card.

Abstract: Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Abstract: Improved parasitic analysis of a design of an electrical circuit (e.g. a PCB coupled to an IC package) can use a first parasitic analysis to identify a first set of pins having excessive parasitic values (“hotspots” in the design) and then identify a second set of pins that do not have excessive parasitic values. The pins in the second set can be clustered (e.g. using a grid of cells) to reduce a model size for calculations in a second parasitic analysis, and the pins in the first set can be analyzed in the second parasitic analysis either individually or in clusters of similar pins with excessive parasitic values.

Abstract: A circuit for controlling a battery includes a switch. The switch includes a source, a gate, and a drain. The drain of the switch is configured to be connected to a positive terminal of the battery. The circuit also includes a first diode. The first diode includes an anode and a cathode. The anode of the first diode is connected to the source of the switch. The cathode of the first diode is connected to the drain of the switch and is configured to be connected to the positive terminal of the battery. The circuit also includes a second diode. The second diode includes an anode and a cathode. The anode of the second diode is configured to be connected to a negative terminal of the battery. The cathode of the second diode is connected to the source of the switch and to the anode of the first diode.

Abstract: Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: A method for building a simulation program with integrated circuit emphasis (SPICE) circuit model of an optical coupler is provided. The method includes: providing a plurality of electrical parameters of the SPICE circuit model of the optical coupler circuit for a plurality of temperature values, and building the SPICE circuit model of the optical coupler at each of the temperature values according to the electrical parameters of the optical coupler for each of the temperature values, so as to form a plurality of temperature-independent SPICE circuit models of the optical coupler; forming a plurality of temperature-voltage conversion switch circuit elements by utilizing control of a voltage source and temperature characteristics of an impedance; and connecting the temperature-voltage conversion switch circuit elements to the temperature-independent SPICE circuit models of the optical coupler, respectively, so as to build a temperature characterized SPICE circuit model of the optical coupler.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Abstract: Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin.

Abstract: A power storage device 20 comprises: a plurality of power storage elements C1-C6 that are connected in series; energy transfer circuits 40 provided respectively to the plurality of power storage elements C1-C6; a common bus 50 to which the energy transfer circuits 40 of the plurality of power storage elements C1-C6 are commonly connected; and a control device 70. Each energy transfer circuit 40 includes one or a plurality of switching transformers Tr, each switching transformer having a first winding 41A that is connected to the power storage elements C1-C6 and a secondary winding 41B that is connected to the common bus 50. The control device 70 uses the switching transformers Tr of the energy transfer circuits 40 to transfer energy between the power storage elements via the common bus 50, thereby equalizing the voltages of the power storage elements C1-C6. The common bus 50 is in an electrically floating state.