Abstract: An energy storage apparatus includes a plurality of energy storage devices connected in series, a voltage detection circuit that detects voltages of the plurality of energy storage devices, and a discharge circuit that discharges the energy storage devices individually, and a BMU having a control unit, in which the control unit discharges only an energy storage device having a highest voltage among the plurality of energy storage devices. Further, charging is stopped when a first duration elapses in a state that a cell voltage of the energy storage device having the highest voltage exceeds a first voltage threshold, or charging is stopped when a second duration elapses in a state that the cell voltage of the energy storage device having the highest voltage exceeds a second voltage threshold.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Abstract: An automated system and method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The system operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The system inspects the various devices and automatically traces DC circuit paths to DC power rails. The system then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The system generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: The application relates to direct current, DC, charging cable including two DC conductors configured for transmitting electrical energy between an electrical vehicle and a charging device, at least a signal line having a first signal line end and a second, opposite signal line end and a control device, the first signal line end is connected at a first connection point to one of the DC conductors, and the control device is configured for measuring a voltage difference between the second signal line end and a second connection point of the one of the DC conductors distant to the first connection point for determining a temperature of the DC charging cable.

Abstract: A motherboard having a smart charging function is provided. A connection interface is configured to an electrical device. A first controller is coupled to the switching circuit and communicates with the electrical device via a first transmission path. A second controller is coupled to the switching circuit and communicates with the electrical device via a second transmission path. In a standard charge mode, the first transmission path is turned on and the first controller directs a voltage converter circuit to generate first charge power to the electrical device. In a fast charge mode, the first controller determines whether the electrical device has a specific operating system. Responsive to determining that the electrical device does not have the specific operating system, the second transmission path is turned on and the second controller directs the voltage converter circuit to generate second charge power to the electrical device.

Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.

Abstract: Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Abstract: A battery management method and apparatus is disclosed. The battery management method of a master device includes transmitting, upon a determination of not receiving sensing data of a reference battery cell among a plurality of battery cells included in a first battery module, a request for the sensing data of the reference battery cell to a head slave device of a second battery module, and receiving the sensing data of the reference battery cell from the head slave device of the second battery module, wherein the sensing data of the reference battery cell is transferred through a tail slave device of the first battery module and a tail slave device of the second battery module.

Abstract: A battery cell evaluation apparatus is provided that includes a current source configured to output a current at a frequency, measurement circuitry, and control circuitry. The control circuitry may be configured to electrically connect a cell of a battery to the current source and the measurement circuitry to apply the current across terminals of the cell and receive a measurement of an impedance phase shift of the cell as phase shift data from the measurement circuitry. The control circuitry may also be configured to compare the phase shift data to a protection profile, and trigger a protection device to prevent damage to the battery based on the comparison of the phase shift data to the protection profile.

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

Abstract: This invention provides a technique for suppressing deterioration in the value of a power storage system. This invention provides a monitoring system comprising: a detection unit that detects that a detection value related to a power storage system satisfies a condition; a specifying unit that specifies the type of prohibited action executed in the power storage system that satisfies the condition; and a determination unit that, on the basis of the specified type of prohibited action, calculates the life of the power storage system and/or determines the time over which the power storage system can keep operating after the specification.

Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N ? R 0 , R c = 1 N ? R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.

Abstract: A fixing device and a fixing method for a clock tree are provided. The fixing method for the clock tree includes: performing a clock signal path tracking operation on a netlist of a circuit according to timing constraint information to obtain a clock tree circuitry structure; identifying a convergency status of the clock tree circuitry structure to find out at least one clock convergence point, and setting one of a plurality of clock signals on the clock convergence point as a selected clock signal; performing a fix point identification operation on the clock tree circuitry structure based on the selected clock signal to obtain a plurality of candidate fix points; and calculating a plurality weighting values of the candidate fix points, obtaining a plurality of selected fixed points according to the weighting values.

Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

Abstract: Techniques for noise impact on function (NIOF) reduction for an integrated circuit (IC) design are described herein. An aspect includes receiving a list of victim nets in which NIOF failures are present in an IC design. Another aspect includes attempting NIOF correction in each victim net of the list of victim nets. Another aspect includes, based on a failure of a NIOF correction in at least one victim net of the list of victim nets, saving the at least one victim net to a wire promote/demote list. Another aspect includes updating the list of victim nets based on the NIOF correction. Another aspect includes, based on determining that the updated list of victim nets is empty, promoting or demoting the at least one victim net from the wire promote/demote list in the IC design.

Abstract: An aircraft-based power system includes a charger system that includes a charger controller and a charger circuit. The charger system is further configured to connect to a ground-based power source and the charger system is further configured to deliver power from the ground-based power source to the charger circuit. The charger circuit is configured to be controlled by the charger controller and the charger controller is configured to control the charger circuit consistent with a charging protocol. The charger system is further configured to charge a battery system that includes a plurality of battery cells with the charger circuit consistent with the charging protocol.

Abstract: A power tool includes a receiving device having at least one first and second power consumption element. A power supply unit connectable to the power tool includes a connecting device having at least one first and second power output element, the receiving device being designed to receive and hold the connecting device, so that the power consumption elements and the power output elements are connectable. Both the first and second power consumption elements have a positive pole as well as a negative pole, and both the first and second power output elements have a positive pole as well as a negative pole. The positive pole of the first power consumption element and the positive pole of the second power consumption element as well as the negative pole of the first power consumption element and the negative pole of the second power consumption element are positioned at a distance from each other in at least one first and second direction.

Abstract: A status signal output circuit outputs a first status signal indicating with a binary level whether or not power the storage unit is normal in accordance with a determination result of the status determination circuit, and, as a second status signal, a pulse width modulation (PWM) signal according to the status of the power storage unit when a measurement circuit including the status determination circuit is normal, or a signal having a axed level when the measurement circuit including the status determination circuit is abnormal. A control signal output circuit outputs, to a drive circuit, a control signal for control to bring a switch inserted between the power storage unit and a load into an OFF state when the power storage unit has abnormality, in accordance with the first status signal and the second status signal output from the status signal output circuit.

Abstract: A communication apparatus (1), such as a mobile phone, a tablet computer or a laptop computer, provides charging reminders to the user of a connected peripheral device (14), such as a headset. The charging reminders are provided in dependence on an auxiliary status signal (AS) received from the peripheral device (14) and on detected charging events (ME), wherein a main charging event (ME) comprises a charging or replacement of a main battery (2) that energizes the communication apparatus (1). The auxiliary status signal (AS) indicates an auxiliary energy level (AL) of an auxiliary battery (15) of the peripheral device (14). The communication apparatus (1) detects low-battery conditions (LC), based on the indicated auxiliary energy level (AL), and provides notification signals (NS) for a user interface (11) to notify the user of the detected low-battery conditions (LC) in response to the detected main charging events (ME).