Abstract: A power tool system includes a hand-held power tool having a power tool housing accommodating a motor, and a battery pack interface electrically connected to the motor within the power tool housing. A battery pack includes a battery pack housing accommodating at least one battery cell and a power tool interface electrically connected to the at least one battery cell within the battery pack housing. The power tool interface is configured to be physically and electrically connected to and disconnected from the battery pack interface of the power tool. A wireless communicator is attached to or accommodated within the battery pack housing. The wireless communicator is configured to wirelessly communicate with an external device using radio waves while the power tool interface of the battery pack is physically and electrically connected to the battery pack interface of the hand-held power tool.

Abstract: A sensor system can include a sensor coil and a sensor coupled to the sensor coil. The sensor coil can include coil portions that generate signals based on magnetic coupling induced in the coil portions by a receiving coil device (e.g., a NFC tag) and magnetic distortion induced in the coil portions by magnetic coupling of a power transmitting unit (PTU). The sensor can reduce the magnetic distortion induced in the first and the second coil portions by the PTU, detect the receiving coil device based the first and the second signals, and control the PTU based on the detected receiving coil device.

Abstract: An energy system for a motor vehicle and a method for charging at least one electrical energy storage device of the energy system.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Abstract: Embodiments of the present disclosure disclose a battery management system. In the system, a first microcontroller is connected to a second microcontroller; a battery monitoring module is configured to monitor a state of the battery pack and transmit the state of the battery pack to the first and the second microcontroller respectively via a state signal of the battery pack, and control the state of the battery pack according to a control instruction from the first and the second microcontroller; a sampling control module is configured to detect the state of a high voltage loop of the battery pack, and transmit the state of the high voltage loop to the first and the second microcontroller respectively via a state signal of the high voltage loop of the battery pack, and control the state of the high voltage loop according to a control instruction from the first and the second microcontroller.

Abstract: Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. The processor Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: A battery control device incorporated in a battery system including a battery pack with a plurality of unit cells connected in series and a temperature sensor attached to a predetermined unit cell of the plurality of unit cells. In the battery control device, an integrated amount calculator calculates an integrated amount of current flow since start of current conduction through the battery pack. A temperature acquirer acquires a temperature of the predetermined unit cell detected by the temperature sensor as a temperature of each of the plurality of unit cells on a condition that the integrated amount of current flow calculated by the integrated amount calculator is smaller than a predetermined value.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

Abstract: A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: The invention relates to a system for indicating information representing battery status of an electronic device. The system comprises a charging unit and an electronic device. The charging unit comprises: charging means; wireless communication means; and indication means. The electronic device comprises a rechargeable battery; charging means; and wireless communication means. During the wireless charging of the electronic device the electronic device is configured to detect information representing the battery status of said electronic device and to communicate the detected information representing the battery status to the charging unit, and the charging unit is configured to receive the information from the electronic device and to indicate at least part of the received information representing the battery status of the electronic device. The invention relates also to a method for indicating information representing battery status of an electronic device.

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

Abstract: The present inventions, in one aspect, are directed to techniques and/or circuitry to applying a charge pulse to the terminals of the battery during a charging operation, measure a plurality of voltages of the battery which are in response to the first charge pulse, determine a charge pulse voltage (CPV) of the battery, wherein the charge pulse voltage is a peak voltage which is in response to the first charge pulse, determine whether the CPV of the battery is within a predetermined range or greater than a predetermined upper limit value and adapt one or more characteristics of a charge packet if the CPV is outside the predetermined range or is greater than a predetermined upper limit value.

Abstract: Disclosed is a battery management apparatus, which includes: a precharging unit having a plurality of switches, the precharging unit being connected to the first main relay in parallel and connected between the second main relay and the second charge/discharge terminal; a control unit configured to control the plurality of switches which causes an output voltage of the battery module to be converted into an AC voltage and applied to the first main relay or the second main relay; and a diagnosing unit configured to diagnose a failure of the first main relay based on a first both-end voltage value of the first main relay to which the AC voltage is applied or to diagnose a failure of the second main relay based on a second both-end voltage value of the second main relay to which the AC voltage is applied.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. The cell removal circuit is configured to prevent a defective energy storage cell of the plurality of energy storage cells from causing other energy storage cells of the plurality of energy storage cells to become defective. A method includes receiving power at a charging node of an energy storage array, the energy storage array including a plurality of energy storage cells. Responsive to failure of an energy storage cell of the plurality of energy storage cells, current is provided through the defective energy storage cell, and responsive to the defective energy storage cell becoming an open circuit, discontinuing provision of the current through the defective energy storage cell.

Abstract: An electronic device is provided. The electronic device includes a housing, a battery included within the housing, a connector electrically connected to an external power supply device including an integrated circuit (IC) and exposed to a part of the housing, and a power management unit included within the housing and electrically connected to the connector, wherein the power management unit is configured to communicate with the IC of the external power supply device, and wherein the connector is configured to receive a first current of a first current value during at least a part of the communication and to receive a second current of a second current value greater than the first current value during at least a part in which the communication is not performed.

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.

Abstract: An apparatus for jump starting a vehicle having a battery and an alternator is disclosed.