Abstract: A preparation method of a thin film transistor (TFT) array substrate includes a step of providing a substrate to prepare a light shielding layer and a buffer layer in sequence on the substrate; and a step of preparing an active layer, a gate insulation layer, a gate, an interlayer insulation layer, and a source/drain metal layer in sequence on the buffer layer; wherein a light absorption layer is prepared on one side of the active layer. Absorbing light prevents most of the light from being reflected to the active layer by disposing a black photoresist below a source and a drain or over the light shielding layer, thereby improving performance of TFT devices.

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

Abstract: A display panel and a method for fabricating the same are provided, the display panel including a substrate, a first insulating layer on the substrate, a source-drain layer on the first insulating layer, and a flexible layer pattern. The source-drain layer includes sources and drains. The flexible layer pattern includes at least one opening, the sources and the drains of the display panel are arranged in the openings, and the at least one opening corresponds to at least one of the sources and at least one of the drains.

Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

Abstract: The present application provides a LDMOS transistor having a floating vertical field plate (VFP) and a manufacturing method thereof. The floating VFP comprises a floating field plate polysilicon layer and a laminated structure. The laminated structure comprises a stack of alternate layers of insulating material and ferroelectric material, and in the laminated structure, an outermost layer and an innermost layer are the insulating material. In the present application, the polarization in the ferroelectric material is set in the floating VFP with smaller size, the polarization of the ferroelectric layer enhances the “charge sharing” effect to produce higher breakdown voltage when the transistor is off; and the polarization of the ferroelectric material layer induces more electrons in the drift zone to reduce on resistance when the transistor is on. Accordingly, the increase of breakdown voltage and the reduction of on resistance can be achieved simultaneously.

Abstract: A semiconductor device includes a semiconductor structure, a first dielectric layer and a plurality of multilayer stacks. The semiconductor structure includes conductive features therein. The first dielectric layer is on the semiconductor structure. The multilayer stacks are arranged on the first dielectric layer. Each of the multilayer stacks comprises a semiconductor layer over the first dielectric layer, a conductive layer over the semiconductor layer and a second dielectric layer over the conductive layer. The second dielectric layer includes a top portion and a bottom portion wider than the top portion.

Abstract: The semiconductor device includes: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer including a channel layer and a barrier layer, and a two-dimensional electron gas being formed at an interface between the channel layer and the barrier layer; a source, a gate, and a drain disposed on one side of the semiconductor layer away from the substrate; and at least two drain junction terminals located on the side of the semiconductor layer away from the substrate and disposed at intervals between the gate and the drain, the at least two drain junction terminals being electrically connected to the drain respectively. In the embodiments of the present application, the on-resistance of the device can be reduced while the current collapse phenomenon is eliminated, thereby improving the long-term reliability of the device.

Abstract: Disclosed are a unit pixel of a microdisplay and a method of manufacturing the same. In the unit pixel, each of the sub-pixels forming blue, green, and red light is vertically stacked on the growth substrate. As a result, the area of a unit pixel may be reduced, and transfer processes may be facilitated.

Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.

Abstract: An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.

Abstract: The present disclosure discloses a temperature sensor, a display panel, and a display apparatus, in the field of sensors. The temperature sensor includes a ring oscillator consisting of n levels of phase inverters, where n is an odd number greater than or equal to 1. Each level of phase inverter includes a first thin film transistor (TFT) and a second TFT that are connected in series. An on/off state of the second TFT is configured to be in a normally-on state, an on/off state of the first TFT is configured to be determined by a signal input to the phase inverter, and mobility of an active layer material of the first TFT is greater than mobility of an active layer material of the second TFT.

Abstract: A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool for contacting the die during a transfer from the die supply source to the substrate; a first motion system for moving the bond head along a first axis; and a second motion system, independent of the first motion system, for moving the bond tool along the first axis.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed memory device comprises multiple staircase structures stacked over a substrate. The multiple staircase structures are positioned in a dielectric fill structure over the substrate. Each staircase structure comprises multiple gate electrodes separated by multiple insulating layers. The memory device further comprises a semiconductor channel extending from through the multiple staircase structures into the substrate. A first portion of peripheral via structures extends through the dielectric fill structure and is connected to the gate electrodes of each staircase structure. A second portion of peripheral via structures extend through the dielectric fill structure and is connected to a peripheral device over the substrate and neighboring staircase structures.

Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.

Abstract: A method of manufacturing an electrode layer and a method of manufacturing a capacitor using the same are provided. The method of manufacturing the electrode layer includes performing a first sub-cycle sequentially providing a tin precursor and an oxygen source on a substrate, performing a second sub-cycle sequentially providing a tin precursor, a tantalum precursor, and an oxygen source on the substrate on which the first sub-cycle is performed, and repeating a cycle including the first sub-cycle and the second sub-cycle to form a tantalum-doped tin oxide layer on the substrate. A tantalum concentration in the tantalum-doped tin oxide layer is determined by the tin precursor provided in the second sub-cycle.

Abstract: This invention provides a three-dimensional junctionless neuron network device and a manufacturing method thereof. The device comprises: a substrate; and a stack structure is formed on the surface of the substrate, the stack structure comprises alternately stacked gate electrode layers and isolation layers and has a channel hole penetrating the substrate; a weighting gate layer is formed on the surface of the channel hole, and the weighting gate layer has a gap from the bottom of the channel hole; a gate dielectric layer is located on the weight gate between the layer and the gate electrode layer; a tunneling dielectric layer on the surface of the weighting gate layer; a channel layer filled in the channel hole, the channel layer being in contact with the substrate. The invention adopts a vertically stacked isolation layer and gate layer design. The stack structure has an array of channel holes.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate on which at least one light guide groove is provided, the light guide groove penetrating the substrate; and a light emitting structure disposed on one side of the substrate, the light emitting structure including at least one set of a first electrode and a second electrode. The light guide groove at least corresponds to one set of a first electrode and a second electrode to prevent bad points. A wavelength conversion dielectric layer is filled into the light guide groove to avoid a coffee ring effect and achieve uniform and full-color light emission of a light emitting device. The semiconductor structure may further save manufacturing costs and prevent crosstalk between light emitted from various light emitting units.

Abstract: A light-emitting layer, which is a stack of a first light-emitting layer and a second light-emitting layer, is provided between an anode and a cathode. The first light-emitting layer is formed on the anode side and contains a first light-emitting substance converting triplet excitation energy into light emission, a first organic compound having an electron-transport property, and a second organic compound having a hole-transport property. The second light-emitting layer contains a second light-emitting substance converting triplet excitation energy into light emission, the first organic compound, and a third organic compound having a hole-transport property. The second organic compound has a lower HOMO level than the third organic compound. The first light-emitting substance emits light with a wavelength shorter than that of light emitted from the second light-emitting substance. The first and the second organic compounds form an exciplex. The first and the third organic compounds form an exciplex.

Abstract: The present invention provides an amorphous silicon thin film transistor and a manufacturing method of the amorphous silicon thin film transistor, which comprise: a substrate, a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, an N+-doped layer, a protective insulating layer, and a passivation layer. The N+-doped layer is disposed between the active layer and the source/drain electrode layer. The protective insulating layer is disposed on the source/drain electrode layer. A channel is formed in the source/drain electrode layer and penetrates the N+-doped layer and the protective insulating layer. The passivation layer covers the channel and the protective insulating layer. The protective insulating layer and the source/drain electrode layer are flush with each other in the channel.