Patents Examined by Moin Rahman
  • Semiconductor device, semiconductor package, method for manufacturing semiconductor device, and method for manufacturing semiconductor package
    Patent number: 9564364
    Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 7, 2017
    Assignee: Shinko Electric Industries Co., LTD.
    Inventor: Takaharu Yamano
  • System, method and apparatus to relieve stresses in a semiconductor wafer caused by uneven internal metallization layers
    Patent number: 9564404
    Abstract: Systems and methods for forming semiconductor wafers with wafer support structures includes: multiple semiconductor devices formed in multiple semiconductor dies. An electrical interconnect structure is formed over the semiconductor devices and providing electrical connections to the semiconductor devices. The electrical interconnect structure includes multiple metallization layers. At least one portion of at least one metallization layer includes variations in density of conductive lines or conducting devices as compared to the other portions of the metallization layers. At least one wafer support structure is formed substantially across a width of the semiconductor wafer. The semiconductor wafer being thinned to between about 40 um and about 200 um after the semiconductor devices formed thereon.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 7, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Manuel A. d'Abreu
  • Method of manufacturing semiconductor device and method of maintaining deposition apparatus
    Patent number: 9564316
    Abstract: A method of manufacturing a semiconductor device, includes forming an aluminum compound film on a surface of a process chamber by supplying an aluminum (Al) source to the process chamber, the surface contacting the aluminum source in the process chamber; disposing a wafer on a susceptor provided in the process chamber after forming the aluminum compound film; and forming a thin film for the semiconductor device on the wafer.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Yul Lee, Sang Heon Han, Seung Hyun Kim, Jang Mi Kim, William Solari, Hyun Wook Shim, Suk Ho Yoon
  • Organic light emitting device and method of manufacturing the same
    Patent number: 9548471
    Abstract: Disclosed is an organic light emitting device and a method of manufacturing the same, wherein the organic light emitting device is decreased in its thickness, and also decreased in its radius of curvature so as to realize the flexible device, and the organic light emitting device comprising a first component including a first plurality of layers, the first plurality of layers including a thin film transistor layer deposited on a surface of a first substrate, an emitting component layer deposited on the thin film transistor layer, and a passivation layer deposited on the emitting component layer; a second component including a second plurality of layers that are deposited on a surface of a second substrate without using an adhesive; and an adhesion layer between the first component and the second component, the adhesion layer coupling together the first component and the second component.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 17, 2017
    Assignee: LG Display Co., Ltd.
    Inventor: Chang Nam Kim
  • Method of fabricating a semiconductor structure with a self-aligned contact
    Patent number: 9543203
    Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chia-Hsun Tseng, Wei-Hao Huang, Yu-Ting Hung
  • Interconnect routing configurations and associated techniques
    Patent number: 9542522
    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Dae-Woo Kim
  • Method of making a light emitting device and a light emitting device made thereof
    Patent number: 9543464
    Abstract: The method includes preparing a plurality of light-emitting units, one of the plurality of light-emitting units comprising an electrode, a light-emitting stack, and a protection layer with a first part covering the electrode and a second part which comprises a portion surrounding the electrode and covers the light-emitting stack; removing the portion without removing the first part; forming a wavelength conversion layer on the first part and the light-emitting stack not covered by the second part; and removing the first part to substantially expose the electrode.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: January 10, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Ming-Chi Hsu, Chih-Ming Wang, Chien-Yuan Wang
  • Selective local metal cap layer formation for improved electromigration behavior
    Patent number: 9536779
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Recess with asymmetric walls and method of fabricating the same
    Patent number: 9536922
    Abstract: A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the substrate, wherein the recess comprises a first wall, a second wall and a bottom. A patterned mask is formed to cover the substrate. Part of the top surface adjacent to the second wall is exposed through the patterned mask. Finally, the substrate is removed to form a sloping wall, wherein the sloping wall, the first wall and the bottom form a recess with asymmetric walls.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: January 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Lai, Chih-Hong Wu, Feng-Ying Hsu
  • Semiconductor devices including a channel pad, and methods of manufacturing semiconductor devices including a channel pad
    Patent number: 9525065
    Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a channel pad on the channel insulating layer. The channel pad has a curved upper surface. Methods of manufacturing semiconductor devices are also provided.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Min Kyeon, Woong Seop Lee, Jin Hyun Shin
  • Image sensor
    Patent number: 9515120
    Abstract: An image sensor includes a substrate with a unit pixel defined by a first separation pattern, a photoelectric conversion part in the substrate, a photocharge storage in the substrate, the photocharge storage being adjacent to the photoelectric conversion part, a second separation pattern between the photoelectric conversion part and the photocharge storage, a shielding part on a bottom surface of the substrate to cover the photocharge storage, the shielding part including a first protrusion extending into the substrate and toward the first separation pattern, and an extension extending from the first protrusion to cover the bottom surface of the substrate; and an anti-reflection layer between the shielding part and the substrate, the anti-reflection layer having an overhang structure between the first protrusion and the extension.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changyong Um, Youngwoo Jung, Jungchak Ahn
  • Compound semiconductor device having gallium nitride gate structures
    Patent number: 9502524
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Wen Hsiung
  • Silicon wafer and method of manufacturing thereof, and method of manufacturing semiconductor device
    Patent number: 9502266
    Abstract: An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer 11 whose nitrogen concentration is 1×1012 atoms/cm3 or more or whose specific resistance is 20 m?·cm or less by boron doping, and an epitaxial layer 12 provided on the wafer 11. On the wafer 11, if a thermal treatment is performed at 750° C. for 4 hours and then at 1,000° C. for 4 hours, polyhedron oxygen precipitates grow predominantly over plate-like oxygen precipitates. Therefore, in the device processes, plate-like oxygen precipitates cannot be easily formed. As a result, even when the LSA treatment is performed after various thermal histories in the device processes, it is possible to prevent the dislocation, which is triggered by oxygen precipitates, from generating.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 22, 2016
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Jun Fujise
  • Light emitting diode chip, light emitting device, and wafer-level structure of light emitting diode
    Patent number: 9502614
    Abstract: A light emitting device is provided with a growing base having specific geometry to prevent delamination between the encapsulant and the growing base, and thereby enhance structural reliability of the light emitting device. Furthermore, the light emitting efficiency as well as uniformity of light output of the light emitting device can be improved by forming the side surface of the growing base with at least a curved portion or slanted portion, and uneven structures can be formed on the curved portion or slanted portion to further improve the uniformity of light output. Furthermore, the light emitting diode chips can be fabricated by taking batch processing on the growing substrate, as provided in the wafer-level structure, with the advantages of saving cost, improving yield, etc.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 22, 2016
    Assignee: FORMOSA EPITAXY INCORPORATION
    Inventors: Chun-Wei Chen, Jen-Chih Li, Shyi-Ming Pan
  • Metal gate structure for midgap semiconductor device and method of making same
    Patent number: 9496143
    Abstract: A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by including an annealed layer of relatively thick TiN to dominate and shift the overall work function down from that of PFET. The structure has a PFET base covered with a high-k dielectric, a layer of annealed TiN, a layer of unannealed TiN, a thin barrier over the unannealed TiN, and n-type metal over the thin barrier.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hoon Kim, Kisik Choi
  • Graded buffer epitaxy in aspect ratio trapping
    Patent number: 9496347
    Abstract: A method of forming a semiconductor device includes: providing a patterned structure comprising a silicon substrate and dielectric stacks deposited on the silicon substrate, the dielectric stacks forming trenches exposing a plurality of surface portions of the substrate within the trenches; forming one or more epitaxial buffer layers within the trenches on the exposed surface portions of the substrate; and growing a semiconductor material on the epitaxial buffer layer that is the furthest away from the substrate; wherein each of the one or more epitaxial buffer layers and the semiconductor material has less than about 3% lattice mismatch to the layer immediately beneath the one or more epitaxial buffer layer and the semiconductor material.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Amlan Majumdar, Kuen-Ting Shiu, Jeng-Bang Yau
  • Solid-state imaging device, manufacturing method thereof, and electronic apparatus
    Patent number: 9490293
    Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 8, 2016
    Assignee: Sony Corporation
    Inventor: Takayuki Enomoto
  • Solid-state imaging device and electronic device
    Patent number: 9478569
    Abstract: The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: October 25, 2016
    Assignee: Sony Corporation
    Inventors: Yusuke Uesaka, Atsuhiko Yamamoto
  • Organic light emitting display
    Patent number: 9478767
    Abstract: An organic light emitting display includes a first substrate comprising a major surface, and a pixel array formed over the major surface of the first substrate. The pixel array comprises a plurality of pixels formed over the first substrate and a plurality of spacers arranged over the first substrate. Each pixel comprises a first electrode and an organic emission layer formed over the first electrode. The pixel array provides a plurality of recesses and a plurality of bumps, and the plurality of recesses correspond to the first electrodes of the plurality of pixels and the plurality of bumps corresponds to the plurality of spacers.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: October 25, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hee-Chul Jeon
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 9472682
    Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: October 18, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Junichi Koezuka, Toshinari Sasaki