Abstract: A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is to the electrode having a reflective property, the longer the wavelength of light emitted from the light-emitting layer is.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract: Integrated circuits with bipolar transistors are provided. In one embodiment, a bipolar transistor may include an emitter region, a first base region that surrounds the emitter region, a collector region that surrounds the first base region, and a second base region that surrounds the collector region. Respective well taps may be formed within the emitter, collector, and the second base regions. A deep doped well having the same doping type as the base regions may extend beneath the emitter, collector, and base regions. In another embodiment, the bipolar transistor may include an emitter region, a base region that surrounds the emitter region, and a collector region that surrounds the base region. Respective well taps may be formed within the emitter, base, and collector regions. A deep doped well having the same doping type as the base region may extend beneath the emitter and only a portion of the base region.

Abstract: Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.

Abstract: A light-emitting element with which a reduction in power consumption and an improvement in productivity of a display device can be achieved is provided. A technique of manufacturing a display device with high productivity is provided. The light-emitting element includes an electrode having a reflective property, and a first light-emitting layer, a charge generation layer, a second light-emitting layer, and an electrode having a light-transmitting property stacked in this order over the electrode having a reflective property. The optical path length between the electrode having a reflective property and the first light-emitting layer is one-quarter of the peak wavelength of the emission spectrum of the first light-emitting layer. The optical path length between the electrode having a reflective property and the second light-emitting layer is three-quarters of the peak wavelength of the emission spectrum of the second light-emitting layer.

Abstract: One portion of a first insulator film, which is positioned on a second semiconductor region, and another portion of the first insulator film, which is positioned on a third semiconductor region, are removed, while a first portion of the first insulator film, which is positioned on a first semiconductor region is remained, one portion of a second insulator film, which is positioned on the first semiconductor region, and another portion of the second insulator film, which is positioned on the second semiconductor region, are removed, while a second portion of the second insulator film, which is positioned on the third semiconductor region is remained, and a metal film that covers the first portion, the second semiconductor region, and the second portion, and the second semiconductor region are caused to react with each other and a metal compound layer is formed.

Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.

Abstract: Doping metal oxide charge transport material with an organic molecule lowers electrical resistance while maintaining transparency and thus is optimal for use as charge transport materials in various organic optoelectronic devices such as organic photovoltaic devices and organic light emitting devices.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

Abstract: Methods and apparatus relating to providing a collection grid suitable for use in PV modules. The disclosed collection grid may be at least partially applied to a protective laminate sheet in a manner that removes the high temperature requirements of conventional screen printed collection grids, to avoid unwanted heat-related deformation of the laminate sheet.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

Abstract: A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.

Abstract: Arrangements of pixel components that allow for full-color devices, while using emissive devices that emit at not more than two colors, and/or a limited number of color altering layers, are provided. Devices disclosed herein also may be achieved using simplified fabrication techniques compared to conventional side-by-side arrangements, because fewer masking steps may be required.