Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Abstract: Provided is a semiconductor device that can improve yield and non-defective rate by obtaining the thickness of a melt-bonding material and suppressing inclination of a circuit board. The semiconductor device includes a circuit board including a circuit pattern layer, a semiconductor element mounted on the circuit board, a melt-bonding portion arranged on an upper surface of the circuit pattern layer, a bonding lead including a bonding portion facing the upper surface of the circuit pattern layer and electrically connected to the circuit pattern layer via the melt-bonding portion, and a pressing portion directly contacted with an upper surface of the circuit board.

Abstract: A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a single-crystal first semiconductor, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode is opposed to the N-well region via a gate insulating film. The single-crystal first semiconductor is provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor. The second semiconductor is provided on the first semiconductor and includes P-type impurities.

Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.

Abstract: An optical sensor includes a light-emitter device formed in a body of solid-state material with wide band gap having a surface. The light-emitter device includes a cathode region having a first conductivity type and an anode region having a second conductivity type. The anode region extends into the cathode region from the surface of the body. The anode region and the cathode region define a junction, and the cathode region has, near the junction, a peak defectiveness area accommodating vacancies in the crystalline structure due to non-bound ions or atoms of Group IV or VIII of the periodic table, which may include carbon, silicon, helium, argon, or neon. The vacancies are at a higher concentration with respect to mean values of vacancies in the anode region and in the cathode region. For example, the vacancies in the peak defectiveness area have a concentration of at least 1013 atoms/cm?3.

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip.

Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

Abstract: Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material.

Abstract: A semiconductor device includes a substrate, a semiconductor layer positioned above the substrate, and a blocking structure positioned between the substrate and the semiconductor layer. A dimension of the blocking structure is greater than a dimension of the semiconductor layer. The blocking structure may suppress diffusion of impurities from layers below the blocking structure.

Abstract: A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

Abstract: A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

Abstract: An electromagnetic wave absorption sheet is arranged to contact an upper surface and side surfaces of an electronic component mounted on a wiring board, a heat conduction plate is arranged to contact the electromagnetic wave absorption sheet, a heat transfer sheet is arranged to contact the heat conduction plate, and a heat dissipation member is arranged to contact the heat transfer sheet. Heat conductive particles contained in the heat transfer sheet contact a flat surface portion of the heat conduction plate. The electromagnetic wave absorption sheet, the heat conduction plate, and the heat transfer sheet are interposed between the heat dissipation member and the electronic component, as a heat conduction member for conducting heat generated in the electronic component and the like to the heat dissipation member.

Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

Abstract: A current sensor device may include a routable molded lead frame that includes a molded substrate. The current sensor device may include a conductor and a semiconductor chip mounted to the molded substrate. The semiconductor chip may include a magnetic field sensor that is galvanically isolated from the conductor by the molded substrate and is configured to sense a magnetic field created by current flowing through the conductor. The current sensor device may include one or more leads configured to output a signal generated by the semiconductor chip. The one or more leads may be galvanically isolated from the conductor by the molded substrate.