Patents Examined by Nathan W. Ha
  • Semiconductor package and method of manufacturing the same
    Patent number: 11069588
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Oh, Hyun-ki Kim, Sang-soo Kim, Seung-hwan Kim, Yong-kwan Lee
  • Semiconductor device with multiple threshold voltage and method of fabricating the same
    Patent number: 11056486
    Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Hui-Cheng Chang
  • Method for reducing contact resistance in semiconductor structures
    Patent number: 11043597
    Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz
  • Self-aligned gate edge trigate and finFET devices
    Patent number: 11043492
    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Biswajeet Guha, Tahir Ghani, Christopher N. Kenyon, Leonard P. Guler
  • Three-dimensional semiconductor device
    Patent number: 11024638
    Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Il Shim, Kyung Dong Kim, Ju Hak Song, Jee Hoon Han
  • Semiconductor device and method of manufacturing a semiconductor device
    Patent number: 11018067
    Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 25, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Kyeong Tae Kim, Yi Seul Han, Jae Beom Shim, Tae Yong Lee
  • Display device
    Patent number: 11009756
    Abstract: A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 18, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Shuji Nishi, Takashi Satoh
  • Magnetoresistive devices and methods therefor
    Patent number: 11004899
    Abstract: A magnetoresistive device may include a first ferromagnetic region, a second ferromagnetic region, and an intermediate region positioned between the first ferromagnetic region and the second ferromagnetic region. The intermediate region may be formed of a dielectric material and comprise at least two different metal oxides.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Jijun Sun
  • Interface structures and methods for forming same
    Patent number: 10998265
    Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 10991678
    Abstract: The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of reducing the uppermost semiconductor chip damage and stably performing wire bonding even if an excessive force is applied during a die bonding process or a wire bonding process, and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 27, 2021
    Inventors: Jung Hak Kim, Hee Jung Kim, Se Ra Kim, Jung Ho Jo, Kwang Joo Lee, Seung Hee Nam, Young Kook Kim
  • Semiconductor devices and fabrication methods thereof
    Patent number: 10971405
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Microfabricated ultrasonic transducer having individual cells with electrically isolated electrode sections
    Patent number: 10967400
    Abstract: An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Butterfly Network, Inc.
    Inventors: Susan A. Alie, Keith G. Fife, Joseph Lutsky, David Grosjean
  • Integrated circuit including multi-height standard cell and method of designing the same
    Patent number: 10957683
    Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seong Lee, Ah-Reum Kim, Min-Su Kim, Jong-Kyu Ryu
  • Vertical memory devices
    Patent number: 10950624
    Abstract: A vertical memory device includes gate electrodes on a substrate and a channel. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes, and includes a first portion, a second portion and a third portion. The second portion is formed on and connected to the first portion, and has a sidewall slanted with respect to the upper surface of the substrate so as to have a width gradually decreasing from a bottom toward a top thereof. The third portion is formed on and connected to the second portion.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Cheon Baek, Ji-Ye Noh, Yoon-Hwan Son, Ji-Sung Cheon
  • Image pickup element, method of manufacturing image pickup element, and electronic apparatus
    Patent number: 10950644
    Abstract: An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Sony Corporation
    Inventors: Shuji Manda, Susumu Hiyama, Yasuyuki Shiga
  • Semiconductor storage device
    Patent number: 10943949
    Abstract: A semiconductor storage device includes a plurality of memory cells and a first circuit. The first circuit is configured to read data from a subset of the memory cells, such as a page unit or the like, then determine whether the data as read from the subset contains an error. The first circuit calculates a bit error rate for the subset if the subset contains an error and performs a recovery processing on the subset if the calculated bit error rate is less than a first threshold value but greater than a second threshold value.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yosuke Kobayashi
  • Semiconductor device
    Patent number: 10943899
    Abstract: A semiconductor device includes a guard active area formed in a substrate, a plurality of transistors disposed in an element area adjacent to the guard active area, each of the transistors including an active area and a gate structure crossing the active area, and a diode transistor disposed between a first transistor and a second transistor among the transistors, and having a diode gate structure connected to the guard active area, a first active area connected to a gate structure of the first transistor, and a second active area connected to a gate structure of the second transistor.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Jeong Kim, In Mo Kim
  • Semiconductor device and method for manufacturing the same
    Patent number: 10930574
    Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Integrated circuit (IC) device
    Patent number: 10930649
    Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
  • Methods of forming an apparatus for making semiconductor dieves
    Patent number: 10930548
    Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim