Abstract: A MEMS device includes a movable section, a frame, a beam, and an electrode substrate. The frame surrounds a surrounding of the movable section. The beam extends from at least a part of the frame, and is connected to the movable section. The electrode substrate includes a fixed electrode, an extended electrode, and a substrate section. The fixed electrode is formed on the electrode substrate in at least a part of a region facing a swing section. The extended electrode is connected to the fixed electrode, and is formed on the electrode substrate in at least a part of a region facing the shaft.

Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.

Abstract: A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

Abstract: A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires is forming the closed polygon and surrounding the center. The first and second wires are interlaced, and none of the first wires and second wires are coupled to each other.

Abstract: A light-emitting display device includes a substrate having a plurality of pixels. A first electrode is provided on the substrate for each pixel, and a pixel defining layer defines each of the pixels. The pixel defining layer has an opening to expose the first electrode. A charge injection layer is on the first electrode, and a surface processing layer is on the charge injection layer. The surface processing layer extends from inside the opening of the pixel defining layer to a top surface of the pixel defining layer. The surface processing layer including a plurality of grooves in a portion extending on the top surface of the pixel defining layer. A charge transport layer is on the surface processing layer, a light-emitting layer is on the charge transport layer, and a second electrode is on the light-emitting layer.

Abstract: A p-type semiconductor layer containing a solid solution of NiO and ZnO as a principal component is joined to an n-type semiconductor layer containing ZnO as a principal component, and the p-type semiconductor layer contains a rare earth element R. The content of the rare earth element R is preferably 0.001 to 1 mole with respect to 100 moles of the principal component. Further, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb can be used as the rare earth element, for example. An internal electrode 4 is preferably principally composed of a composite oxide containing the rare earth element R and Ni. Thereby, photoelectric conversion efficiency can be improved, and ultraviolet light can be directly detected as a photocurrent without externally disposing a power source circuit.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the barrier region is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region includes a first barrier partial region, wherein a distance between the first barrier partial region and the drift region is a first distance, and a second barrier partial region, wherein a distance between the second barrier partial region and the drift region is a second distance which is longer than the first distance. The second barrier partial region is in contact with a side surface of an insulated trench gate.

Abstract: A thin film transistor (TFT) array substrate includes a first substrate, a plurality of TFTs formed on the first substrate, a color filter layer covered on the TFTs, and a plurality of pixel electrodes corresponding to the TFTs. The color filter layer is directly formed on the TFTs. The color filter layer includes a plurality of photoresist units. Each of the pixel electrodes is to electrically connected to a drain of the TFT via an opening.

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract: According to one embodiment, a magnetic memory device includes a first stack structure including a first magnetic layer, and a first nonmagnetic layer provided on the first magnetic layer, a second stack structure including a second magnetic layer provided on the first nonmagnetic layer, a second nonmagnetic layer provided on the second magnetic layer, and a top conductive layer provided on the second nonmagnetic layer, and a sidewall conductive layer provided on a sidewall of the second stack structure.

Abstract: Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer.

Abstract: Described herein are elements for light emitting devices comprising: an emissive element comprising a host material and an emissive guest material and substantially free of light scattering material; and a light scattering element comprising either a non-emissive or an emissive material, wherein the light scattering element is between about 2.5% to about 60% by volume voids and the thickness ratio of light scattering element to the emissive element is at least 1 to about 2.

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract: In order to reduce the source resistance in a field effect semiconductor device, an electron injection layer, which causes a band-to-band tunnel current to flow between a source electrode and a channel forming layer of which the central portion is a channel layer, is provided on the channel forming layer on the side in contact with the channel layer.

Abstract: Systems and methods are disclosed for manufacturing a CMOS-MEMS device (100). A partial protective layer (401) is deposited on a top surface of a layered structure to cover a circuit region. A first partial etch is performed from the bottom side of the layered structure to form a first gap (501) below a MEMS membrane (207) within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate (215) within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the circuit region of the layered structure and also prevents the second partial etch from damaging the CMOS circuit component (211).

Abstract: A static random access memory (SRAM) including at least a SRAM cell is provided. A gate layout of the SRAM cell includes first to fourth strip doped regions, a recessed gate line and first and second gate lines. The first to fourth strip doped regions are disposed in the substrate in order and separated from each other. The recessed gate line intersects the first to fourth strip doped regions. The first to fourth strip doped regions are disconnected at intersections with the recessed gate line. The first gate line intersects the first and the second strip doped regions. The first and the second strip doped regions are disconnected at intersections with the first gate line. The second gate line intersects the third the fourth strip doped regions. The third and the fourth strip dopeds region are disconnected at intersections with the second gate line.

Abstract: The present invention provides a diamond semiconductor device which includes: a diamond substrate; a diamond step section disposed over substrate surface of the diamond substrate having a {001} crystal face to rise substantially perpendicularly to substrate surface; an n-type phosphorus-doped diamond region; and a diamond insulation region. In the diamond step section, a first step section having a {110} crystal face over a side surface is integrated with a second step section having a {100} crystal face over a side surface. The phosphorus-doped diamond region is formed by crystal growth started from base angle of the step shape of the first step section over the side surface of the first step section and substrate surface of the diamond substrate as growth base planes. The diamond insulation region is formed by crystal growth over the side surface of the second step section and substrate surface of the diamond substrate as growth base planes.

Abstract: In a method according to embodiments of the invention, a light emitting structure comprising a plurality of light emitting diodes (LEDs) is provided. Each LED includes a p-contact and n-contact. A first mount and a second mount are provided. Each mount includes anode pads and cathode pads. The anode pads are aligned with the p-contacts and the cathode pads are aligned with the n-contacts. The method further includes mounting the light emitting structure on one of the first and second mounts. An electrical connection on the first mount between the plurality of LEDs differs from an electrical connection on the second mount between the plurality of LEDs. The first mount is operated at a different voltage than the second mount.

Abstract: A semiconductor device incorporating a heat spreader and improved to inhibit dielectric breakdown is provided. The semiconductor device has an electrically conductive heat spreader having a bottom surface, a sheet member having a front surface and a back surface electrically insulated from each other, IGBTs and diodes fixed on the heat spreader and electrically connected thereto, and a molding resin. The front surface contacts with the bottom surface and has a peripheral portion jutting out from edges thereof. The molding resin encapsulates the front surface of the sheet member, the heat spreader and the semiconductor elements. At least part of the back surface of the sheet member is exposed out of the molding resin. The heat spreader has, at a corner of its bottom surface, corner portions having a beveled shape or a curved-surface shape as seen in plan and having a rectangular shape as seen in section.

Abstract: A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.