Abstract: Disclosed is a single-chip twin light source light emitting device including a first epitaxial layer, a substrate, and a second epitaxial layer. The first epitaxial layer includes a first n-type semiconductor layer with a n-type conducting structure, a first light emitting layer with a multi-quantum well structure, and a first p-type semiconductor layer with a p-type conducting structure. The second epitaxial layer includes a second n-type semiconductor layer with a n-type conducting structure, a second light emitting layer with a multi-quantum well structure, and a second p-type semiconductor layer with a p-type conducting structure. Therefore, the light emitting device can emit one-color or two-color light by controlling the first epitaxial layer and the second epitaxial layer respectively.

Abstract: Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.

Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.

Abstract: In a transmission line via structure, a plurality of sub-structures are stacked in a via through the substrate along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion, an outer conductor portion, and at least one dielectric support member. The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume between the outer conductor portion and the center conductor portion. Conductive paste is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.

Abstract: An organic light emitting diode (OLED) display device and a display panel thereof are provided. The organic light emitting diode display panel comprises a first substrate, a first electrode, an organic light emitting layer, a second electrode, and a second substrate. The first electrode is disposed on the first substrate. The organic light emitting layer is disposed on the first electrode. The second electrode is disposed on the organic light emitting layer. The second substrate is located on the second electrode. The material of the second electrode comprises an alkaline earth element and silver. The second electrode comprises a first portion and a second portion, and the first portion is located between the second portion and the first substrate. The ratios of the alkaline earth element to silver in the first portion and in the second portion are different.

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.

Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Abstract: A method of fabricating a carbon nanotube array sensor includes the following steps. A carbon nanotube array, a first electrode and a second electrode are provided, the carbon nanotube array includes a plurality of carbon nanotubes. Each of the carbon nanotubes includes a first end and a second end opposite to the first end. A first metallophilic layer is formed on the first end of each of the carbon nanotubes. At least one first conductive metal layer is arranged between the first metallophilic layer and the first electrode to electrically connect each of the carbon nanotubes with the first electrode. A second metallophilic layer is formed on the second end of each of the carbon nanotubes. At least one second conductive metal layer is arranged between the second metallophilic layer and the second electrode to electrically connect each of the carbon nanotubes with the second electrode.

Abstract: An electronic component (100), which comprises a substrate (1), at least one first electrode (3) arranged on the substrate (3) and a growth layer (7) on the side of the electrode (3) remote from the substrate (7), wherein the electrode (7) arranged on the growth layer (3) comprises a metal layer (9) with a thickness of less than or equal to 30 nm and the growth layer (7) has a thickness which is less than or equal to 10 nm. An electrical contact is also disclosed.

Abstract: Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.

Abstract: A light emitting device having a wavelength converting layer. The light emitting device includes a substrate; a semiconductor stack having a first conductive-type semiconductor layer, an active layer and a second conductive-type semiconductor layer disposed on the substrate; a first wavelength converting layer covering a top of the semiconductor stack; and a second wavelength converting layer disposed on the first wavelength converting layer and having a width narrower than the first wavelength converting layer. The second wavelength converting layer is employed, thereby being capable of reducing a color variation according to a viewing angle.

Abstract: Disclosed is a method for manufacturing an array substrate, comprising: step A, sequentially forming patterns of a first conduction layer, source and drain electrodes, an active layer, and an insulation layer on one side of the substrate, wherein at least one via hole is provided on the insulation layer; step B, sequentially forming a gate metal layer and a passivation layer on the substrate on which the first conduction layer, the source and drain electrodes, the active layer, and the insulation layer have been formed, wherein the gate metal layer comprises a gate electrode and a gate line, and the gate metal layer is coupled to the first conduction layer through the at least one via hole to form a path for dispersing static electricity.

Abstract: Methods for producing a continuous hole in a substrate are provided. A laser is used for producing an inner proportion and a diffuser of the continuous hole, wherein an angular position of the laser with respect to the substrate is changed at least three times.

Abstract: Pixel electrodes have end portions inclined at inclination angles ?, where 30°???85°, relative to a substrate surface of a substrate. An organic layer disposed on the pixel electrodes is formed by vapor deposition using deposition beams that enter the substrate surface at incident angles ? smaller than 90°??max, where ?max is the maximum inclination angle among the inclination angles of the end portions of the pixel electrodes, under a deposition substrate temperature condition lower than the glass transition temperature of the organic layer.

Abstract: Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different.

Abstract: Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of Inx3Aly3Gaz3N (x3+y3+z3=1, z3>0).

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate.

Abstract: A method of manufacturing an organic light emitting diode display according to an exemplary embodiment of the present invention includes: forming a first electrode on a substrate; forming an insulation layer on the first electrode; etching the insulation layer to expose the first electrode so as to form a pixel defining layer having the same height as the first electrode; forming an organic layer including one or more emission layers on the first electrode of a sub-pixel region defined by the pixel defining layer by applying a laser-induced thermal imaging (LITI) method; and forming a second electrode on the organic layer.

Abstract: A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.