Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.

Abstract: A semiconductor device includes: a first GaN based semiconductor layer (hereinafter abbreviated as GaN layer); a second GaN layer on the first GaN layer and having a bandgap larger than that of the first GaN layer; a source electrode on the second GaN layer; a drain electrode on the second GaN layer; a gate electrode between the source electrode and the drain electrode, a gate insulating film between the gate electrode and the first GaN layer, a film thickness of the second GaN layer between the gate electrode and the first GaN layer being thinner than that of the second GaN layer between the source electrode and the first GaN layer; and a p-type third GaN layer between the second GaN layer and an end portion on the drain electrode side of the gate electrode, the gate insulating film between the gate electrode and the third GaN layer.

Abstract: A semiconductor light-emitting device includes a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes a periphery surface surrounding the active layer; a plurality of vias penetrating the semiconductor stack to expose the first semiconductor layer; and a patterned metal layer formed on the plurality of vias and covered the periphery surface of the first semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate.

Abstract: To enhance a semiconductor device. A semiconductor device has a plurality of p+-type semiconductor regions disposed between the mutually adjacent two gate trenches, in a cell region. The p+ type semiconductor regions are disposed spaced apart from each other, in plan view, in a p-type body layer in a portion positioned between the mutually adjacent two gate trenches. Any of a p-type impurity concentration in each of the p+ type semiconductor regions is higher than the p-type impurity concentration in the p-type body layer.

Abstract: The disclosure provides an organic light-emitting device. The organic light-emitting device includes a substrate, and an organic light-emitting pixel array disposed on the substrate. The organic light-emitting pixel array includes a plurality of pixels. Each pixel includes a first sub-pixel and a second sub-pixel. Each sub-pixel includes a first electrode, an organic light-emitting element, a second electrode, and an optical path adjustment layer. The optical path adjustment layer is disposed between the first electrode and the second electrode. Particularly, the thickness of the optical path adjustment layer of the first sub-pixel is substantially equal to the thickness of the optical path adjustment layer of the second sub-pixel.

Abstract: A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.

Abstract: A semiconductor light-emitting element includes a substrate, a first metal layer, a second metal layer, a translucent conductive layer, and a semiconductor layer with a light-emitting region. The translucent conductive layer includes an end face intersecting a plane orthogonal to the thickness direction of the substrate. The substrate includes an end face intersecting a plane orthogonal to the thickness direction. The end face of the translucent conductive layer is located inwardly of the end face of the substrate as viewed in the thickness direction.

Abstract: Methods and apparatus for post treating an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, the oxide layer is formed by thermal oxidation or plasma oxidation and treated with a plasma comprising helium. The helium-containing plasma may also include hydrogen, neon, argon and combinations thereof. In one or more embodiments, a SiO2 oxide layer is formed on a silicon substrate and treated with a plasma to improve the interface between the silicon substrate and the SiO2 oxide layer.

Abstract: Disclosed herein are a rectifying device and a method of fabricating the same. The rectifying device includes a first electrode formed in a flat shape, an insulating layer deposited on the first electrode and a second electrode formed on a preset region of the insulating layer in a nanaopillar shape in a longitudinal direction to be asymmetrical to the first electrode, thereby increasing current flow.

Abstract: Disclosed is a composite substrate, which is provided with an inorganic insulating sintered substrate, which has a heat conductivity of 5 W/m·K or more, and a volume resistivity of 1×108 ?·cm or more, and a single crystal semiconductor film, or a composite substrate, which is provided with the inorganic insulating sintered substrate, a single crystal semiconductor film, and a thin layer configured of at least one kind of material selected from among an oxide, a nitride, and an oxynitride, said thin layer being provided between the inorganic insulating sintered substrate and the single crystal semiconductor film. According to the present invention, a low-cost composite substrate with suppressed metal impurity contamination can be provided using an inorganic insulating sintered body, which is opaque to visible light, and which has excellent heat conductivity, and furthermore, a small loss in a high frequency region.

Abstract: An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. The signal line may extend parallel to the surface. The coupling line may extend parallel to the signal line and may be arranged between the surface and the signal line.

Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.

Abstract: A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode.

Abstract: An organic light emitting diode (OLED) display device and a display panel thereof are provided. The organic light emitting diode display panel comprises a first substrate, a first electrode, an organic light emitting layer, a second electrode, and a second substrate. The first electrode is disposed on the first substrate. The organic light emitting layer is disposed on the first electrode. The second electrode is disposed on the organic light emitting layer. The second substrate is located on the second electrode. The material of the second electrode comprises an alkaline earth element and silver. The second electrode comprises a first portion and a second portion, and the first portion is located between the second portion and the first substrate. The ratios of the alkaline earth element to silver in the first portion and in the second portion are different.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract: A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material.

Abstract: A solar cell is discussed. The solar cell according to an embodiment includes a semiconductor substrate, a first conductive type region and a second conductive type region disposed on the same side of the semiconductor substrate, wherein at least one of the first and second conductive type regions includes a main region and a boundary region disposed at a peripheral portion of the main region, and the boundary region has at least one of a varying doping concentration and a varying doping depth.