Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; an insulating layer formed on the second semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; and a gate electrode formed on the insulating layer. The insulating layer is formed of a material including an oxide and is formed by laminating a first insulating layer and a second insulating layer in a positioning order of the first insulating layer followed by the second insulating layer from a side of the second semiconductor layer, and an amount of hydroxyl groups included in per unit volume of the first insulating layer is less than an amount of hydroxyl groups included in per unit volume of the second insulating layer.

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, a plurality of vertical gate columns, and control circuitry. The plurality of word lines is electrically coupled to the plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips. The plurality of word lines including a first word line and a second word line adjacent to each other. The plurality of vertical gate columns is between the plurality of stacks of conductive strips. The plurality of vertical gate columns includes a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line. The first set of vertical gate columns is staggered relative to the second set of vertical gate columns.

Abstract: A semiconductor light-emitting device comprises a semiconductor stack comprising a side, a first surface and a second surface opposite to the first surface, wherein the semiconductor stack further comprises a conductive via extending from the first surface to the second surface; a transparent conductive layer formed on the second surface; a first pad portion and a second pad portion formed on the first surface and electrically connected to the semiconductor stack; and an insulating layer formed between the first pad portion and the semiconductor stack and between the second pad portion and the semiconductor stack.

Abstract: The present disclosure provides MEMS devices and their fabrication methods. A first dielectric layer is formed on a first substrate including integrated circuits therein. One or more first metal connections and second metal connections are formed in the first dielectric layer and are electrically connected to the integrated circuits. A second dielectric layer is formed on the first dielectric layer. An acceleration sensor is formed in the second dielectric layer to electrically connect to the one or more first metal connections. A second substrate is bonded to the second dielectric layer. One or more first metal vias are formed in the second substrate and in the second dielectric layer to electrically connect to the second metal connections. A pressure sensor is formed on the second substrate to electrically connect to the first metal vias.

Abstract: The present invention relates to a substrate stacked image sensor having a dual detection function, in which when first to fourth photodiodes are formed in a first substrate, a fifth photodiode is formed in a second substrate, and the substrates are stacked and combined with each other, the first to fourth photodiodes and the fifth photodiode are combined with each other to obtain a complete photodiode as an element of one pixel, and signals individually detected in each photodiode are selectively read or added to be read according to necessity.

Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.

Abstract: A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, a first dielectric layer, source trace, first source vias, a second dielectric layer, a source pad, and second source vias. The first dielectric layer covers the source electrodes, the drain electrodes, and the gate electrodes. The source traces are disposed on the first dielectric layer, are electrically connected to the source electrodes, and are covered by the second dielectric layer. The source pad is disposed on the second dielectric layer, and includes a first source trunk, a first source branch, and a source sub-branch. The first source branch is protruded from the first source trunk and is electrically connected to one of the drain traces through the second source vias. The source sub-branch is protruded from the first source branch and is electrically connected one of the source electrodes through the third source vias.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.

Abstract: A present MEMS device includes: a semiconductor substrate in which a trench is formed; a functional element that is provided in the trench of the semiconductor substrate and includes a connection electrode; a structural member that forms a cavity surrounding the functional element; a lid portion that includes a conductive member electrically connected to the connection electrode and covers the cavity; an insulating layer that covers the main surface of the semiconductor substrate provided with the lid portion and a semiconductor circuit element; a first electrode that penetrates the insulating layer and is electrically connected to the conductive member; a second electrode that penetrates the insulating layer and is electrically connected to the semiconductor circuit element; and wiring that is provided on a surface of the insulating layer and brings the first electrode and the second electrode into electrical connection to each other.

Abstract: A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or length of the nanorods on the substrate, and wherein the as-deposited nanorods are aligned such that their long-axis is aligned preferentially in the plane of current flow in the electronic switching device.

Abstract: This invention discloses an AC-type vertical light emitting element and fabrication method thereof, which achieves polarity reversal of two LEDs via regional laser stripping and die bonding. The two LEDs are placed on a conductive substrate (e.g. Si substrate); therefore, the bonding pads of the two LEDs are on the back of the conductive substrate and the light emitting surfaces of the two LEDs, thus overcoming such problems of low light emitting efficiency and high thermal resistance of the traditional lateral structure.

Abstract: A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier.

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract: A wavelength conversion element includes a phosphor layer including phosphor particles configured to be excited by light from a light source and a matrix located among the phosphor particles; and a column-shaped structural body including at least two kinds of column-shaped bodies periodically arranged and in contact with the phosphor layer. The column-shaped bodies have different heights and/or different thicknesses. The column-shaped structural body is a photonic crystal.

Abstract: A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.

Abstract: The invention relates to a device comprising a substrate supporting a matrix of diodes organized in rows and columns, and a peripheral substrate contact is arranged on at least one side of the matrix, characterized in that the substrate comprises one or several buried conducting lines having no direct electrical connection with the peripheral substrate contact and being positioned between at least two adjacent columns of diodes and between at least two adjacent rows of diodes.

Abstract: A display device includes a pixel unit including a plurality of pixels coupled to a plurality of control lines and to a plurality of power lines to commonly receive same control signals and power source, a plurality of inlet pads positioned outside the pixel unit, the plurality of inlet pads being configured to apply the power source to the plurality of power lines, a pad bar electrically coupling the plurality of inlet pads, and a plurality of coupling patterns contacting end portions of the plurality of power lines and corresponding end portions of the pad bar, the plurality of coupling patterns electrically connecting the plurality of power lines and the pad bar, and one or more of the end portions of the pad bar and the ends portions of the plurality of power lines have different contact areas with the plurality of coupling patterns.

Abstract: A device including at least one heterostructure p/n diode, including a substrate based on HgCdTe including for each diode: a first part having a first cadmium concentration; a concentrated part, having a second cadmium concentration, greater than the first concentration, forming a heterostructure with the first part; a p+ doped zone situated in the concentrated part and extending into the first part, forming a p/n junction with an n-doped position of the first part, or a base plate; and the concentrated part is only located in the p+ doped zone and forms a substantially constant cadmium concentration well.

Abstract: An organic light emitting diode (OLED) and a method of manufacturing the same. An auxiliary layer comprising a high density metallic compound and an emission layer are formed by a laser induced thermal imaging (LITI) process. The LITI process reduces manufacturing costs and time by eliminating the need for a mask patterning process. The metallic compound has a density of 2 g/cm3 or greater to promote adhesion and improve interfacial planarization. This results in improved luminance uniformity (i.e. luminance mura) between pixels within an OLED display device.