Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.

Abstract: A semiconductor device comprising: a semiconductor chip (10) which is subjected to face-down bonding, having a plurality of electrodes (12) aligned on a straight line (L); a substrate (20) on which is formed an interconnect pattern (22) having bonding portions (24) to which the electrodes (12) of the semiconductor chip (10) are connected and lands (26) electrically connected to the bonding portions (24); external electrodes (30) passing through the substrate (20) and connected to the lands (26); and a support formed from bumps (11, 21) provided between the semiconductor chip (10) and substrate (20), wherein the connected electrodes (12) and bonding portions (24) and the support formed by the bumps (11, 21) maintain the semiconductor chip (10) and substrate (20) substantially parallel.

Abstract: A flip-chip bonding structure on substrate for flip-chip package application is proposed, on which solder bumps can be bonded for electrically coupling a flip chip to the substrate. The proposed flip-chip bonding structure is characterized in that its solder-bump pads can be dimensionally-invariable irrespective of a positional deviation in solder mask due to misalignment. Moreover, the proposed flip-chip bonding structure can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that neighboring solder bumps would be less likely short-circuited to each other and flip-chip underfill can be more easily implemented.

Abstract: A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are farmed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: An insulating layer (3) is formed on a Si wafer (1). An opening portion is made in this insulating layer (3), and subsequently a rerouting layer (2) is formed. Next, a resin layer (4) is formed on the rerouting layer (2). The resin layer (4) is then cured so that the rerouting layer (2) and a Cu foil (5) are bonded to each other through the resin layer (4). Thereafter, a ring-like opening portion (4a) is made in the resin layer (4), and a Cu plating layer (8) is formed inside this opening portion (4a).

Abstract: The present invention provides a ball grid array (“BGA”) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.

Abstract: An electrode structure for a semiconductor device and a method for forming the electrode structure, and a mounted body including the semiconductor device are provided in which the semiconductor device can be easily connected to a circuit board with high reliability. An aluminum electrode is formed on an IC substrate. A passivation film is formed on the IC substrate so as to cover the peripheral portion of the aluminum electrode. A bump electrode is formed on the aluminum electrode by a wire bonding method. An aluminum oxide film is formed on the surface of the aluminum electrode that is exposed around the bump electrode. A conductive adhesive is applied as a bonding layer to the tip portion of the bump electrode of the semiconductor device by a transfer method or a printing method. The semiconductor device is aligned in the face-down state in such a manner that the bump electrode abuts on a terminal electrode of a circuit board, and is provided on a circuit board.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A semiconductor device comprises a plurality of substrates (10) disposed to be stacked one another and having interconnect patterns (12) formed on the substrates, and semiconductor chips (20) mounted on the substrates (10). The interconnect pattern (12) has a bent portion (16) projecting from a surface of the substrate (10). The bent portions (16) are stacked one another and electrically connected.

Abstract: A method is provided for die bonding a semiconductor device to a substrate, which method provides adequate and consistent bondline thickness and assures that the die is spaced from the substrate a predetermined amount. Embodiments include removably attaching a flexible spacer of a predetermined thickness, such as a strip of paper or plastic, to the bonding pad of a substrate, such as an organic lead frame, so that it partially covers the bonding pad while leaving other parts of the bonding pad exposed. Die attach material, such as epoxy paste, is then applied to the exposed areas of the bonding pad, and a die is placed over the bonding pad in contact with the epoxy and the spacer. Due to the presence of the spacer, the die cannot sink when it is placed on the epoxy paste, resulting in a consistent bondline thickness equal to the spacer thickness.

Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.

Abstract: A method for forming a metal interconnection filing a contact hole or a groove having a high aspect ratio. An interdielectric layer pattern having a recessed region corresponding to the contact hole or the groove is formed on a semiconductor substrate, and a barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer, thereby exposing the barrier metal layer formed on the sidewalls and the bottom of the recessed region. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio.

Abstract: An optoelectronic assembly having an insulating substrate with a planar surface and a metal layer bonded to the planar surface such that selected regions of the substrate are exposed and a step is produced between the substrate and a top surface of the metal layer. An active optical device is mounted on the metal layer and a passive optical device is aligned with the active device using the step as a fiduciary for positioning the former. The metal layer provides an electrical path to the active device. The thickness of the metal layer is selected such that the heat generated by the active device is dissipated, the substrate does not interfere with the propagation of light along the first optical axis, and such that the in-plane coefficient of thermal expansion (CTE) of the metal layer is constrained by the substrate. The optoelectronic assembly is also suitable for mounting active devices provided with submounts or without.

Abstract: A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.

Abstract: A circuit assembly is provided with a lower die and an upper die offset and stacked on the lower die. A supporting material, such as a dielectric molding compound or epoxy resin, is dispensed along the side surfaces of the lower die under the overhanging parts of the upper die to provide support for the upper die, thereby preventing cracking of the upper die during wire bonding.

Abstract: A method of maintaining z-height of an integrated circuit component, such as a multi-chip module, a chip or a die, and of visualizing alignment of an integrated circuit package during positioning of an integrated circuit component, is disclosed. The method maintains the z-height of an integrated circuit component during a solder reflow step by applying high-melting solder balls to interconnect pads on the package substrate surface. Such high-melting solder balls, for instance 90 Pb/10 Sn, do not collapse at temperatures sufficient to accomplish reflowing. The high-melting solder balls also make convenient visualization marks for alignment of the package substrate on an integrated circuit component placement tool, such as a die placement tool. A package substrate bearing high-melting solder balls in a pre-determined pattern is easily aligned by an integrated circuit placement tool using machine vision.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate a blanket first dielectric layer. There is then formed upon the blanket first dielectric layer a blanket etch stop layer. There is then formed upon the blanket etch stop layer a patterned first photoresist layer which defines a location of a via to be formed through the blanket etch stop layer and the blanket first dielectric layer to access the contact region. There is then etched while employing a first etch method the blanket etch stop layer to form a patterned etch stop layer.

Abstract: A method of fabricating a semiconductor device on a semiconductor wafer of the type having a plurality of active layers that includes the steps forming a layout for at least one of the active layers where the layout contains a plurality of active region segments and a plurality of inactive regions. The layout is then modified by adding a plurality of dummy active segments in the inactive regions. The layout is further modified by removing a plurality of sub-regions from the active regions to form a plurality of sub-inactive regions. The semiconductor wafer is then processed using the modified layout to provide an environment during the processing of the active layer wherein the relative area of the active to the inactive regions is substantially equal across the wafer.