Abstract: A multiple quantum well light emitting compositional semiconductor device ch as a laser diode or a light emitting diode has an active region comprising an alternating sequence of layers of well layer material and of barrier layer material. The thickness of the barrier layer and of the adjacent well layers is chosen such that for one type of charge carrier a relatively high probability exists for such charge carriers to be present in the barrier region whereas the other type of charge carriers are localized in the potential wells. In this way it is possible to reduce the probability of non-radiative Auger recombination processes occurring thus reducing the threshold current and increasing the quantum efficiency of the device.

Abstract: A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

Abstract: A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions.

Abstract: Position-sensitive radiation detector provided with a semiconductor structure comprising a wafer of semiconductor material of a first conductivity type having two principal surfaces situated at relatively short distances from each other, the dimensions of which are sufficient to enclose the desired radiation detection surface. An electrode structure is formed on the wafer surfaces such that when suitable voltages are applied to said electrodes two drift fields are generated in the depleted body of the wafer. Detector/amplifier circuits are connected to selected electrodes of the electrode structure to emit, during operation, a start signal at the instant at which charge carriers are generated in the depleted part of the structure as a consequence of incident radiation or elementary particles, and to emit a stop signal at the instant when charge carriers reach a detection electrode of the structure after propagation through both drift fields.

Abstract: A class of intermetallic compound contact materials for III-V semiconductors is obtained by depositing successively and concurrently a thin film of a transition metal and a Group III metal upon the semiconductor and annealing the resultant structure, so resulting in the formation of a monocrystalline intermetallic contact. The contacts are stable at temperatures ranging from 600-900.degree. C. and may be fabricated by conventional vacuum deposition.

Abstract: A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively close to the gate signal input area.

Abstract: A solid-state image sensing device has an overflow drain structure for purging superfluous charges. The overflow drain structure includes a gate electrode (34), channel regions (35), and a drain region (32) formed inside each groove (26) formed on a main surface of a semiconductor substrate (6). Optoelectro transducer (4) are formed on main surface regions of the semiconductor substrate continuous with each groove. The drain region is formed on side walls and a bottom wall of each groove by oblique ion implantation. The overflow drain structure formed inside the groove occupies a reduced area on the main surface of the semiconductor substrate and increases its opening ratio.

Abstract: An array [10] of photodetecting active regions [16] includes a layer of photoresponsive material [14] differentiated into a plurality of photodetecting active regions. The layer has a composition which varies across a thickness of the layer from a first surface of the layer to a second surface [14a] of the layer such that a magnitude of an effective energy bandgap of the layer decreases from the first surface to the second surface. A resulting crystal potential field constrains photoexcited minority charge carriers to exist within a region of the layer which is substantially adjacent to the second, narrower energy bandgap surface. The array further includes a plurality of groove structures [18] formed within the second surface of the layer and extending into the layer to a depth less than the thickness of the layer. A groove is interposed between at least two adjacent active regions for substantially preventing minority carriers from laterally diffusing between active regions.

Abstract: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

Abstract: In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed.

Abstract: A monolithically integratable transistor circuit for limiting transient positive high voltages on an electric conductor includes a pnp transistor being conductive only upon exceeding a predetermined potential threshold value being positive as compared with a reference potential. The pnp transistor has an emitter terminal connected to an electric conductor, a collector terminal connected to the reference potential, and a base terminal. A parallel circuit is connected between the base terminal and the electric conductor. The parallel circuit has a high-impedance resistor and a first capacitor. A second capacitor is connected between the base terminal and the reference potential.

Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.

Abstract: A method of passivation of Hg.sub.1-x Cd.sub.x Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embodiments provide sulfide conversion by immersion of the oxide coated Hg.sub.1-x Cd.sub.x Te in a sodium sulfide solution in water with optional ethylene glycol and the selenidization by immersion in a solution of sodium selenide plus sodium hydroxide in water and ethylene glycol. Also, infrared detectors incorporating such sulfide and selenide passivated Hg.sub.1-x Cd.sub.x Te are disclosed.

Abstract: A semiconductor device includes at least one field effect transistor integrated monolithically on a substrate with a decoupling diode between a d.c. supply conductor and a ground conductor. The transistor is preferably a MESFET formed in a first semiconductor layer of the n-type preferably made of a III-V material. According to the invention, the decoupling diode is constituted by the ground conductor forming a Schottky junction of large surface area polarized in the opposite sense with a second semiconductor layer of the n-type, the supply conductor being resistively connected to the second semiconductor layer. According to a preferred embodiment, the second layer also comprises the resistive load of the transistor.

Abstract: A resonant-tunneling heterojunction bipolar transistor (RHBT) device having a superlattice structure and a PN junction. The RHBT includes an emitter layer, a base layer, a collector layer facing the base layer to form a PN junction at the interface between the base layer and the collector layer, and a superlattice structure including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough. The superlattice is formed at least in the emitter layer and faces. The RHBT has a differential negative resistance characteristic for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer.

Abstract: A FET structure has first and second active areas separated by an inactive area with a gate bus located thereon. Gate fingers extend from the gate bus between source and drain contacts on the active areas. Bridges extend over the gate bus and interconnect the source contacts.

Abstract: A semiconductor element is formed in a composite substrate constructed by fixing two semiconductor substrates in close contact with each other, and crystal defects are formed in that portion of at least one of the two semiconductor substrates which lies near the junction plane of the two semiconductor substrates. The crystal defects act as the center of the recombination of excess minority carriers accumulated in an active region of the semiconductor element.

Abstract: An EPROM array has plural rows of split gate transistors, where each transistor includes a floating gate and the floating gate has corner portions. A bit-line defining edge is formed on each floating gate between two of the corners. The bit-line defining edges of first and second floating gates respectively belonging to first and second rows are patterned so that these edges protrude into opposed side areas of a bit line implant window. This arrangement minimizes resistance changes in the bit lines due to mask misalignment. The misalignment insensitivity permits relaxation of dimensional constraints. Cells of the memory array can be drawn to have smaller areas.

Abstract: A wafer of neutron transmutation doped silicon having a pn junction between extended opposite surfaces is formed with bevelled edges. A plurality of reverse biased signal contacts is disposed on one surface to provide an integrated array of avalanche photodiodes.

Abstract: An insulated-gate field-effect transistor device characterized by the channel region consisting of the intermediate heavily doped portion (50; 72) and two lightly doped portions (46, 48; 74,76) provided on both sides of the heavily doped portion. Such a field-effect transistor device is advantageous in that it provides a surface potential locally increased to act as an energy barrier to minority carriers. This permits control over the threshold voltage of a MOS transistor or over the punch-through current of a punch-through transistor without having recourse to the use of a high carrier density throughout the channel region. The carrier density of the channel region being rather reduced, not only reduction in leakage current but improvement in withstand voltage characteristics can be achieved in a device according to the present invention.