Abstract: A semiconductor service having a group III-V compound semiconductor layer formed on a buffer structure for intercepting propagation of defects, in which the buffer structure comprises a first material layer of a group III-V compound semiconductor material, a second material layer of a group III-V compound semiconductor material provided on the first material layer, the second material layer containing a first group III element and a second group III element different from the first group III element with a graded compositional profile in which the content of the second group III element is decreased towards an upper boundary and a lower boundary of the second material layer.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.

Abstract: Methods, and products formed by such methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additive metallization processes. A second mask (26) is formed over portions of the first mask (24) and the interconnect (12). Sidewalls of the first mask (24) which define at least one side of side of said interconnect (12) serve to also define at least one side of said conductive pillar (16). The second mask (26) also defines at least one side of the conductive pillar (16). The conductive pillar (16) is formed by additive metal deposition processes. The conductive pillar (16) is thus self-aligned to the interconnect (12) on which it is formed.

Abstract: A solid-state imaging device includes on a semiconductor substrate of a first conductivity type, a well of the opposite conductivity type and, in addition, a plurality of light-sensitive elements formed in the well. A reverse bias voltage applied to the semiconductor substrate with respect to the well causes charge stored in the light-sensitive elements less than or equal to a potential barrier voltage to leak out into the semiconductor substrate. On the substrate a detection circuit detects the resistance of the semiconductor substrate and a setting circuit sets the reverse bias voltage in such a manner as to keep the potential barrier voltage constant, based on the resistance detected by the detection circuit.

Abstract: An ultraviolet-light sensitive photodiode device comprises a first semiconductor photodiode for producing a first current when illuminated by light and a second semiconductor photodiode for producing a second current when illuminated by light. The first and second photodiodes are electrically connected to produce a signal proportional to the difference between the first and second currents. The first and second photodiodes are substantially equal in sensitivity to visible and infrared light, while the first photodiode is more sensitive to ultraviolet light than the second photodiode. Thus, the photosensitive device resulting from connecting the two photodiodes has a spectrally narrow sensitivity to ultraviolet light.

Abstract: A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region of the opposite conductivity type in the substrate and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs. A separate overflow channel region of the opposite conductivity type is in the substrate at said surface and extends from each of the CCD channel region phases to the adjacent drain region.

Abstract: A photosensor with improved performance is provided with a gate electrode structure for a field effect transistor that includes a semiconductor layer photosensitivity. The gate electrode can be constituted with a kind of metal or a low resistance semiconductor in conjunction with a semiconductor area with photosensitivity adjacent thereto. As a photosensitive semiconductor, amorphous silicon can be used because of its comparatively easy manufacturing method and its high sensitivity. As a field effect transistor, a thin film transistor of amorphous silicon can be used to correspond to the demand for making transistors over a large area. A MOSFET is preferably used as a field effect transistor for the improvement of sensitivity and speed of the sensor.

Abstract: A semiconductor device and a circuit suitable for use in an intelligent power switch include an insulated gate field effect transistor (IGFET) (T2) and a power semiconductor switch (T1). The insulated gate field transistor IGFET (T2) is provided by a semiconductor body (6) which has a first region (7) of one conductivity type adjacent a given surface (6a) of the semiconductor body with the first region (7) forming at least part of a conductive path to a first main electrode of the power semiconductor switch. A second region (8) of the opposite conductivity type is provided within the first region adjacent the given surface (6a) and a third region (11) of the one conductivity type is provided adjacent the given surface (6a) within the second region (8), an area of the second region (8) underlying an insulated gate (14) provided on the given surface (6a) for defining a conduction channel (15) providing a gateable connection between the third region (11) and a fourth region (12) of the one conductivity type.

Abstract: An interline area image sensor structure with particular doping arrangements which provides an effective antiblooming control and, when a voltage signal is applied to each transfer gate, all the charge collected in a photodiode will be depleted and transferred to an interline CCD.

Abstract: An improved damper diode is obtained by replacing the usual step junction (P.sup.+ -Nu-N.sup.+) structure of the prior art with an epitaxial double sided Pi-Nu structure (i.e., P.sup.+ -Pi-Nu-N.sup.+) in which the thickness and impurity concentrations of the Pi and Nu regions are substantially equal and have a combined thickness about equal to the prior art Nu region for the same voltage. Improved transient response (TFR), better transient energy absorption capability (UIS) and lower forward transient turn-on peak over-shoot voltage (TOPO) is obtained for the same or higher reverse breakdown voltage (BVR), in the same or smaller die size.

Abstract: A means and method for forming improved merged complementary bipolar, complementary MOS (CBICMOS) structures is described. The N-channel and N-base devices are gouped in a first isolated semiconductor region and the P-channel and P-base devices are grouped in a second isolated semiconductor region. The two regions are separated by lateral isolation. By sharing internal device regions and arranging the internal device regions in the proper sequence a particularly compact structure is obtained which may be wired to implement a variety of CBICMOS circuits using a single wiring layer. Both CMOS and vertical NPN and PNP bipolar devices are produced in a common substrate by a common process.

Abstract: A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly affected by a deviation in mask alignment in the manufacturing process. This invention utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deviation in mask alignment. In addition, a construction has been invented in which a current flowing through a portion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this improved construction.

Abstract: There is disclosed a structure for self aligned and non-self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.

Abstract: Receiving sections for receiving light emitting and light receiving elements are formed in a housing. The axes of the light emitting and light receiving elements which are inserted into the receiving sections are optically coupled at a preset angle. Further, light transmission windows are formed in the housing in front of the light emitting and light receiving elements which are inserted into the receiving sections, and the opening area of the light transmission window on the light receiving element side is made smaller than that of the light transmission window on the light emitting element side.

Abstract: A semiconductor device having a high density structure and resistant against external abnormal electric charges is disclosd. The semiconductor device comprises an input diffusion resistor coupled to an external terminal and formed in a semiconductor substrate, a diffusion region formed in the semiconductor substrate and a voltage wiring having a contact portion connected to the diffusion region through at least one contact hole formed in an insulating layer covering the diffusion region. A first distance between a first end of the diffusion region close to the diffusion resistor and a first part of the contact portion nearest to the first end is made larger than a distance between a second end opposite to the first end of the diffusion region and a second part of the contact portion nearest to the second end.

Abstract: A quantum field-effect directional coupler is described comprised of two quantum waveguides closely spaced apart with an adjacent gate electrode over the space between waveguides. The coupling of electron probability density between waveguides is controlled by the voltage applied to the gate electrode. The coupler implements a voltage-controlled current switch. Several couplers can be connected to perform multiplex/demultiplexing functions.

Abstract: A leaky thin film transistor including a charge transport layer, source and drain electrodes located adjacent to the charge transport layer, a gate electrode spaced from the charge transport layer by a gate dielectric layer, the gate electrode defining a gated portion of the charge transport layer extending between the source electrode and the drain electrode, and an ungated portion of the charge transport layer extending between the source and drain electrodes and providing an electrical path for leakage current to flow between the source and drain electrodes in parallel with the gated path between the source and drain electrodes.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascaded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: An optical sensor excellent in reliability and mass producibility and low in cost, by forming a magnetic optical crystal, polarizer and analyzer monolithically on the same substrate.

Abstract: A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the main surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity.