Abstract: A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.

Abstract: A vertical nitride semiconductor device includes an n-type aluminum nitride single-crystal substrate having an Si content of 3×1017 to 1×1020 cm?3 and a dislocation density of 106 cm?2 or less. An ohmic electrode layer is formed on an N-polarity side of the n-type aluminum nitride single-crystal substrate.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.

Abstract: Disclosed is a semiconductor light emitting device, including: a plurality of semiconductor layers grown sequentially on a growth substrate; a first electrode part, which is in electrical communication with the first semiconductor layer and supplies one of electrons or holes thereto; a second electrode part, which is in electrical communication with the second semiconductor layer and supplies the other one of electrons or holes thereto; and a non-conductive reflective film, which is formed on the plurality of semiconductor layers for reflecting the light generated in the active layer towards the growth substrate and has an opening formed therein, wherein at least one of the first and second electrode parts includes a lower electrode exposed at least partly through the opening; an upper electrode provided on the non-conductive reflective film; and an electrical connection, which comes into contact with the lower electrode by passing through the opening and is in electrical communication with the upper electrod

Abstract: A thyristor device that can include a disc-shaped device comprising a semiconductor material forming alternating p-n-p-n type layers. The device can include a gate area extending from an external gate lead contact point to a plurality of thyristor units connected in parallel. Each thyristor unit can include at least one exposed pB layer portion to form at least one plural point to which gate current can be directed. Further, an insulator layer can be formed over the gate area to insulate at least a portion of the gate electrode from the pB layer so that displacement current can be directed to short dots and then to the plural points. Current entering each thyristor unit can generate a turned-on area at each thyristor unit that spreads throughout the thyristor device.

Abstract: A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Abstract: A scalable voltage source having a number N of partial voltage sources implemented as semiconductor diodes connected to one another in series, wherein each of the partial voltage sources has a semiconductor diode with a p-n junction. A tunnel diode is formed between sequential pairs of partial voltage sources, wherein the tunnel diode has multiple semiconductor layers with a larger band gap than the band gap of the p/n absorption layers and the semiconductor layers with the larger band gap are each made of a material with modified stoichiometry and/or a different elemental composition than the p/n absorption layers of the semiconductor diode. The partial voltage sources and the tunnel diodes are monolithically integrated together, and jointly form a first stack with a top and a bottom, and the number N of partial voltage sources is greater than or equal to two.

Abstract: Magnetic random-access memory (RAM) cells and arrays are described based on magnetoresistive thin-film structures.

Abstract: One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.

Abstract: A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

Abstract: After forming a sacrificial gate structure straddling a stacking of a semiconductor mandrel structure and a dielectric mandrel cap and spacers present on sidewalls of the stack, portions of the spacers located on opposite sides of the sacrificial gate structure are removed. Epitaxial source/drain regions are formed on exposed sidewalls of portions of the semiconductor mandrel structure located on opposite sides of the sacrificial gate structure. The sacrificial gate structure is removed to provide a gate cavity. Next, portions of the spacers exposed by the gate cavity are removed to expose sidewalls of a portion of the semiconductor mandrel structure. III-V compound semiconductor channel portions are then formed on exposed sidewalls of the semiconductor mandrel structure. Portions of the semiconductor mandrel structure and the dielectric mandrel cap exposed by the gate cavity are subsequently removed from the structure, leaving only the III-V compound semiconductor channel portions.

Abstract: Disclosed are an organic semiconductor element, a fabrication method thereof, woven and non-woven fabric structures therewith, and a semiconductor device therewith. The organic semiconductor element comprising an organic semiconductor layer; a linear source electrode and a linear drain electrode provided in the organic semiconductor layer and spaced apart from and parallel to each other; a linear gate electrode provided on the organic semiconductor layer to cross the linear source and drain electrodes; and an electrolyte layer in contact with the organic semiconductor layer and the linear gate electrode.

Abstract: In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

Abstract: A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode.

Abstract: A monolithic three-dimensional memory device contains a high mobility metal dichalcogenide channel. A stack of alternating layers comprising first material layers and second material layers is formed over a substrate. A memory opening is formed through the stack of alternating layers. A memory film is formed in the memory opening. A metal dichalcogenide channel is formed on an inner sidewall of the memory film. A dielectric core is formed within the metal dichalcogenide channel. A stack of titanium and gold may be employed to form a drain region to enhance contact. A hafnium oxide, aluminum oxide or hafnium aluminum oxide hafnium aluminum oxide layer may be employed on either side, or on both sides, of the metal dichalcogenide channel to enhance the mobility of electrons in the metal dichalcogenide channel.

Abstract: A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3).

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, a semiconductor film overlapping with the gate electrode with the gate insulating film positioned therebetween, a source electrode and a drain electrode that are in contact with the semiconductor film, and an oxide film over the semiconductor film, the source electrode, and the drain electrode. An end portion of the semiconductor film is spaced from an end portion of the source electrode or the drain electrode in a region overlapping with the semiconductor film in a channel width direction. The semiconductor film and the oxide film each include a metal oxide including In, Ga, and Zn. The oxide film has an atomic ratio where the atomic percent of In is lower than the atomic percent of In in the atomic ratio of the semiconductor film.

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.