Abstract: A light-emitting diode (LED) package includes a light-emitting structure, an optical wavelength conversion layer on the light-emitting structure, and an optical filter layer on the optical wavelength conversion layer. The light-emitting structure includes a first-conductivity-type semiconductor layer, an active layer on the first-conductivity-type semiconductor layer, and a second-conductivity-type semiconductor layer on the active layer, and emits first light having a first peak wavelength. The optical wavelength conversion layer absorbs the first light emitted from the light-emitting structure and emits second light having a second peak wavelength different from the first peak wavelength. The optical filter layer reflects the first light emitted from the light-emitting structure and transmits the second light emitted from the optical wavelength conversion layer.

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Abstract: An electronic device, includes: a graphene nanoribbon having a first graphene and a second graphene; a first electrode coupled to the first graphene; and a second electrode coupled to the second graphene, wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity and the second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity.

Abstract: A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: An adhesive composition includes: a binder component; a photo-initiator component; and an anaerobic-initiator component. The binder component includes a monomer, an oligomer, and a plasticizer; the photo-initiator component includes a photo-radical initiator and a photo-base generator (PBG); and the anaerobic-initiator component includes a metal reactive initiator, an accelerator, and an inhibitor.

Abstract: An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×1015 cm?3.

Abstract: Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×1016 cm?3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

Abstract: Quantum dot layers and display devices including quantum dot layers are described. In an embodiment the quantum dot layer includes quantum dots with metal oxide coatings to adjust the spacing between adjacent quantum dots. In an embodiment, the metal oxide coatings may create a charge transporting matrix, be QD-LED compatible.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: Graphene nanoribbon arrays, methods of growing graphene nanoribbon arrays, and electronic and photonic devices incorporating the graphene nanoribbon arrays are provided. The graphene nanoribbons in the arrays are formed using a seed-mediated, bottom-up, chemical vapor deposition (CVD) technique in which the (001) facet of a semiconductor substrate and the orientation of the seed particles on the substrate are used to orient the graphene nanoribbon crystals preferentially along a single [110] direction of the substrate.

Abstract: A light emitting device is provided. The light emitting device includes a substrate and a plurality of light emitting elements. The light emitting elements are electrically connected on the substrate, each having a light emitting surface. A light-transmissive member is arranged on the light emitting elements and a light-reflective member covers a lateral surface of the light emitting elements and a lateral surface of the light-transmissive member. The plurality of light emitting elements include a plurality of first light emitting elements and a second light emitting element that has an area of the light emitting surface smaller than that of each of the first light emitting elements. The second light emitting element is arranged between the first light emitting elements.

Abstract: A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe) over a substrate, and fabricating a dummy gate stack above a silicon layer formed on the layer of SiGe. Etching the silicon layer defines a channel region below the dummy gate stack. The channel is isolated from the substrate by forming a cavity between the channel region and the substrate below the channel region, the cavity extending over a length of the channel region, wherein the length of the channel region extends from a source region to a drain region below the dummy gate stack. The cavity is filled with an oxide and a low K spacer material to isolate the channel region from the substrate.

Abstract: There is provided a fluorescent material having a composition represented by the following Formula (1). (Sra,Bab,Eux,M11,M2e)SiOf·cMgO . . . Formula (1) (In the formula, M1 is at least one tertiary group element selected from Y and Tb; M2 is an alkali metal selected from Li, Na, and K; and 0<a<2, 0<b<2, 0?c<1, 0.001?d?0.06, 0?e?0.06, 0<x<0.1, and 3.7?f?4.1 are set.) Further, there is provided a light-emitting device including: the fluorescent material; and a light source irradiating the fluorescent material with excitation light to cause the fluorescent material to emit light.

Abstract: An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

Abstract: A light emitting diode includes a first electrode, a second electrode facing the first electrode, and a mixture layer between the first electrode and the second electrode. The mixture layer includes a quantum dot, a hole transporting material, and an electron transporting material.

Abstract: Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.

Abstract: A staircase avalanche photodiode with a staircase multiplication region composed of an AlInAsSb alloy. The photodiode includes a buffer layer adjacent to a substrate and an avalanche multiplication region adjacent to the buffer layer, where the avalanche multiplication region includes a graded AlInAsSb alloy grown lattice-matched or psuedomorphically strained on either InAs or GaSb. The photodiode further includes a photoabsorption layer adjacent to the avalanche multiplication region, where the photoabsorption layer is utilized for absorbing photons. By utilizing AlInAsSb in the multiplication region, the photodiode exhibits a direct bandgap over a wide range of compositions as well as exhibits large conduction band offsets much larger than the smallest achievable bandgap and small valance band offsets. Furthermore, the photodiode is able to detect extremely weak light with a high signal-to-noise ratio.