Patents Examined by Nikolay Yushin
  • Co-integration of elastic and plastic relaxation on the same wafer
    Patent number: 9941355
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Nicolas J. Loubet, Devendra K. Sadana
  • Hybrid vertical cavity light emitting sources
    Patent number: 9941663
    Abstract: Vertical cavity light emitting sources that utilize patterned membranes as reflectors are provided. The vertical cavity light emitting sources have a stacked structure that includes an active region disposed between an upper reflector and a lower reflector. The active region, upper reflector and lower reflector can be fabricated from single or multi-layered thin films of solid states materials (“membranes”) that can be separately processed and then stacked to form a vertical cavity light emitting source.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: April 10, 2018
    Assignees: Wisconsin Alumni Research Foundation, Board of Regents, The University of Texas System
    Inventors: Zhenqiang Ma, Weidong Zhou
  • Light emitting diode with structured substrate
    Patent number: 9941444
    Abstract: Embodiments of the invention include a semiconductor light emitting device. The device includes a substrate having a first surface and a second surface opposite the first surface. The device further includes a semiconductor structure disposed on the first surface of the substrate. A cavity is disposed within the substrate. The cavity extends from the second surface of the substrate. The cavity has a sloped side wall.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 10, 2018
    Assignee: Koninklijke Philips N.V.
    Inventor: Toni Lopez
  • Fast responsive personalized thermometer
    Patent number: 9939334
    Abstract: A thermometer includes a processing unit configured to receive a plurality of timed apart temperature readings from first and second sensors and a processor calculates heat flux value, Q, and obtains values of the heat flux vs. temperature (Q vs. Ts.) as the temperature approaches a steady state. The processor empirically predicts the steady state temperature of the sensor Ts, using the peak value of the values of Q vs. Ts. The processor may also empirically calculate a bias value as a function of the peak value of Q vs. Ts. The bias value represents the difference between the temperature reading (Ts) at steady state and core temperature of the subject and is added to the steady state temperature to arrive at core.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 10, 2018
    Assignee: Medisim, LTD.
    Inventor: Moshe Yarden
  • Metal oxide semiconductor device
    Patent number: 9941414
    Abstract: In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor is prevented.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Plasmonic light emitting diode
    Patent number: 9935239
    Abstract: A light emitting diode includes a square quantum well structure, the quantum well structure including III-V materials. A dielectric layer is formed on the quantum well structure. A plasmonic metal is formed on the dielectric layer and is configured to excite surface plasmons in a waveguide mode that is independent of light wavelength generated by the quantum well structure to generate light.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yaojia Chen, Ning Li, Devendra K. Sadana, Jinghui Yang
  • Methods of forming vertical transistor devices with different effective gate lengths
    Patent number: 9935018
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and second vertical transistor devices, and forming first and second top spacers, respectively, around the first and second VOC structures, wherein the first spacer thickness is greater than the second spacer thickness. In this example, the method also includes performing at least one epitaxial deposition process to form a first top source/drain structure around the first VOC structure and above the first top spacer and a second top source/drain structure around the second VOC structure and above the second top spacer, and performing an anneal process so as to cause dopants in the first and second doped top source/drain structures to migrate into, respectively, the first and second VOC structures.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita, Kangguo Cheng
  • Acoustic transducer and microphone using the acoustic transducer
    Patent number: 9936305
    Abstract: Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 3, 2018
    Assignees: STMICROELECTRONICS S.R.L., OMRON CORPORATION
    Inventors: Takashi Kasai, Shobu Sato, Yuki Uchida, Sebastiano Conti
  • Memory transistor with multiple charge storing layers and a high work function gate electrode
    Patent number: 9929240
    Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 27, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Method for manufacturing graphine film electronic device
    Patent number: 9929237
    Abstract: A GNR is a ribbon-shaped graphene film which includes: five or more (for example, five, seven, or nine) six-membered rings of carbon atoms which are bonded and arranged in line in a short side direction; and a complete armchair type edge structure along a long side direction. By such a constitution, without using a transfer method, there are materialized a highly reliable graphene film which has an armchair type edge structure with a uniform width at a desired value and which enables an electric current on-off ratio of 105 or more that is practically sufficient for exhibiting a desired band gap.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 27, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Junichi Yamaguchi, Shintaro Sato, Hiroko Yamada, Kazuki Tanaka
  • Fabricating method of fin-type semiconductor device
    Patent number: 9923065
    Abstract: In accordance with various embodiments of the disclosed subject matter, a semiconductor device, and a fabricating method thereof are provided. In some embodiments, the semiconductor device comprises: a semiconductor substrate, wherein a plurality of fins are projected on a surface of the semiconductor substrate; and an insulating layer on side walls of the plurality of fins, wherein the insulating layer is located on the surface of the semiconductor substrate, a surface of the insulating layer is lower than top surfaces of the plurality of fins, and a thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: March 20, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinyun Xie, Ming Zhou
  • Semiconductor structure with enhanced withstand voltage
    Patent number: 9923061
    Abstract: A semiconductor structure including a substrate, a buffer layer, a superlattice formed on the buffer layer, the superlattice including a pattern including n layers made of different materials, n being at least equal to 2, each layer including an AlxGayInwBzN type material where x+y+w+z=1, the thickness of each layer being less than the critical thickness thereof, the number of patterns being at least equal to 50, an insert layer wherein the material has a first lattice parameter, a layer of GaN material, wherein the lattice parameter is greater than the first lattice parameter such that the layer of GaN material is compressed by the insert layer.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 20, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alexis Bavard, Matthew Charles
  • Bipolar transistor with superjunction structure
    Patent number: 9917181
    Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Frank Dieter Pfirsch, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Stephan Voss
  • Rectifier diode fault detection in brushless exciters
    Patent number: 9910083
    Abstract: A method of detecting a diode fault in an AC signal rectifier circuit, the AC signal rectifier circuit including a plurality of diodes, and being arranged to supply a rectified output voltage to a load, wherein the method includes the steps of deriving an operating value indicative of the ratio of the voltage magnitudes of a first harmonic frequency and another harmonic frequency of the rectified output voltage across the load; and determining whether a fault has occurred in one or more diodes on the basis of the derived operating value. The first harmonic frequency is preferably the fundamental harmonic frequency, and/or the another harmonic frequency is preferably the 6th harmonic frequency.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 6, 2018
    Assignee: ROLLS-ROYCE PLC
    Inventors: Vaiyapuri Viswanathan, Amit Kumar Gupta, Chandana Jayampathi Gajanayake, Sivakumar Nadarajan
  • Method for manufacturing vertically integrated semiconductor device
    Patent number: 9911822
    Abstract: A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Damian Sojka
  • Image sensor device and manufacturing method thereof
    Patent number: 9905600
    Abstract: The present disclosure provides a method of manufacturing an image sensor device. The method includes: forming an etch stop layer on a first substrate; forming a light-sensing region comprising a light sensing quantum structure being able to detect a wavelength greater than about 1.5 um; forming a semiconductive substrate over the light-sensing region, the semiconductive substrate comprising an active component; forming an isolation structure extended through the light-sensing region; selectively removing the first substrate to expose the etch stop layer; and thinning the etch stop layer thereby exposing the light-sensing region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Yeur-Luen Tu, Tung-I Lin, Cheng-Lung Wu
  • Semiconductor device
    Patent number: 9905563
    Abstract: A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Ohori, Chikashi Hayashi, Manabu Yanagihara
  • Method of associating tire pressure control apparatuses to wheel positions
    Patent number: 9902216
    Abstract: Tire pressure control devices include first sensors to deliver repeatedly a measured value M1 for the rotation speed of the wheel. A measurand, from which the rotation speed of the associated wheel can be derived, is detected in a pointwise manner by means of a second sensor over a predetermined rotation angle ? of the wheel as a function of time, is subjected to a low pass filtering in a subsequent first time interval ?t1 and from the filtered development of the measurand a second measured value M2 is determined, which is a measurement for the rotation speed or respectively for the angular speed of the associated wheel. Each tire pressure control device transmits at the end of a second time interval ?t2 the second measured value M2 together with an identification of the tire pressure control device to a central unit. Comparing M1 and M2 determines wheel position.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: February 27, 2018
    Assignee: HUF HÜLSBECK & FÜRST GMBH & CO. KG
    Inventors: Markus Wagner, Peter Brand, Markus Alexander
  • Thermal conductivity detector circuit and method for operating the same
    Patent number: 9903770
    Abstract: A thermal conductivity detector includes a switch controllable to short-circuit the input of an amplifier to improve the thermal conductivity detector for use in gas chromatography without the need of an additional reference cell, wherein a digital signal processor calculates a transfer function of an analog signal processor from a digitized difference signal received in response to short-circuiting the input of the amplifier at a given time when solely a reference carrier fluid passes through a measuring cell, and the digital signal processor recovers a detector signal by deconvoluting the digitized difference signal with a transfer function.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: February 27, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Glen Eugene Schmidt, Udo Gellert, Aosheng Wang
  • Method of forming nanostructure, method of manufacturing semiconductor device using the same, and semiconductor device including nanostructure
    Patent number: 9899473
    Abstract: Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngtek Oh, Hyeokshin Kwon, Hwansoo Suh, Insu Jeon