Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive one or more power saving signals based at least in part on a selected power saving signal configuration of a set of power saving signal configurations, wherein the UE stores information identifying the set of power saving signal configurations; and perform a power saving operation based at least in part on the one or more power saving signals. In some aspects, a base station may determine one or more power saving signal configurations, of a set of power saving signal configurations, to be used to transmit one or more power saving signals; and transmit the one or more power saving signals using the one or more power saving signal configurations. Numerous other aspects are provided.

Abstract: Techniques are described for power reduction in a computer processor based on detection of whether data destined for input to an arithmetic logic unit (ALU) has a particular value. The data is written to a register prior to performing an arithmetic or logical operation using the data as an operand. Depending on a timing of when the data is supplied to the register, the determination is made before or after the data is written to the register, and a memory associated with the register is updated with a result of the determination. Contents of the memory are used to make a decision whether to allow the ALU to perform the arithmetic or logical operation. The memory can be implemented as a non-architectural register.

Abstract: In an embodiment, an electronic device includes a package power zone controller. The device monitors the overall power consumption of multiple components of a “package.” The package power zone controller may detect workloads in which the package components (e.g. different types of processors, peripheral hardware, etc.) are each consuming relatively low levels of power, but the overall power consumption is greater than a desired target. The package power zone controller may implement various mechanisms to reduce power consumption in such cases.

Abstract: A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Abstract: An information handling system includes multiple power supply units, and first and second chassis management controllers. The power supply units provide power to components within the information handling system. The first chassis management controller calculates a first number of power supply units needed to provide power to the components of the information handling system, and asserts a first chassis armed signal to servers in response to a detection that the first number of power supply units is greater than zero. The second chassis management controller receives the first number of power supply units from the first chassis management controller, and asserts a second chassis armed signal to the servers in response to a detection that the first number of power supply units being greater than zero.

Abstract: Provided are an electronic apparatus, a power-saving control method, and a program capable of realizing both ease of use for a user and power-saving. A determination unit that determines whether a non-operation state of a user continues for a reference time in a first power mode, a mode control unit that shifts a power mode to a second power mode in which power is saved in a case where determination is made that the non-operation state continues for the reference time in the first power mode, a time interval detection unit that detects a time interval from the shift to the second power mode to an operation by the user, and a time control unit that changes the reference time based on the detected time interval are provided.

Abstract: An information handling system may connect to a remote client to display a user interface of the information handling system on a display of the remote client while the information handling system is in a pre-boot stage. The information handling system may transmit user interface data to the remote client for display of the user interface on the remote client. The information handling system may filter the user interface data to remove private information from the user interface data before transmitting the user interface data to the remote client.

Abstract: The invention relates to power over data cable (PoC) systems comprising power source equipment, PSE, and plural PoC devices connected to the PSE. The PoC devices can operate in various power modes including low and high power modes. A method of managing power performed by a processing device of the system upon starting-up includes: reading, in memory of the processing device, a power change record to determine if, prior to the start-up, a target PoC device was about to switch from the low power mode to the high power mode; if it was about to switch, restricting it to remain in the low power mode; otherwise, triggering the target device to switch to the high power mode. As being restricted to the low power mode, the target device can no longer cause power failures. Thus endless loops of power failures caused by one and the same device are avoided.

Abstract: First data is transmitted from a modem of a device to a processor of the device over a point-to-point serial data link at a first one of a plurality of link speeds, where the first data is received at the device over a wireless network connection. The data link transitions to an inactive state following transmission of the first data. Second data is identified that has likewise been received over a wireless network connection, where at least a portion of the second data is received at the device while the data link is in the inactive state. A change from the first speed to a second one of the plurality of link speeds is determined based on historical parameters and predictive parameters. The data link is transitioned to an active state operational at the second link speed to transmit the second data to the processor over the data link.

Abstract: An electronic apparatus includes a first processor configured to restrict direct memory access by one or more peripheral circuits to a volatile memory, and thereafter make a transition from an active state to a sleep state, and a second processor configured to, after the first processor has been brought into the sleep state, set the volatile memory into a self-refresh mode in which a refresh circuit of the volatile memory periodically rewrites data stored in the volatile memory, and thereafter reboot the electronic apparatus.

Abstract: A computer system includes a client device; and a display device operationally connected to the client device, wherein the display device provides the client device with an operating energy, and the display device detects the type of the client device, and, when the client device belongs to a predefined group of client devices, provides the client device with an operating energy even if the display device enters an energy-saving mode or is switched off.

Abstract: Various methods and apparatus for graphics processing are disclosed. In one aspect, a method of graphics processing using a computing system is provided. The method includes booting the computing system. After booting the computing system operating video memory of the computing system at a non-overclocked frequency, and prior to rebooting having the computing system sequentially increment the frequency of video memory by a selected change in frequency through a series of overclocked frequencies, after each frequency incrementing writing data to the video memory and testing the stability of the video memory data writing, and if the stability testing fails then decrementing the frequency of the video memory to a previous overclocked frequency at which the stability testing did not fail.

Abstract: A utilization factor controller is to estimate power consumption values corresponding to a plurality of first utilization factor and second utilization factor pairs, the first utilization factor corresponding to utilization of the first transceiver that is to communicate using a first protocol, the second utilization factor corresponding to utilization of the second transceiver that is to communicate using a second protocol different form the first protocol, the utilization factor controller to select a first utilization factor and second utilization factor pair based on the estimated power consumption value. A transmission time controller is to calculate first and second transmission times to be used by the first and second transceiver based on the selected first utilization factor and second utilization factor pair. A data allocator is to allocate data for transmission by the first transceiver and the second transceiver according to the first and second transmission times.

Abstract: The disclosed computing device may include electronic components, at least one of which is a processor. The computing device may also include a heat sink thermally coupled to the electronic components, as well as a temperature sensor that determines the current temperature inside the computing device. The computing device may further include a controller. The processor may generate a load schedule for the electronic components based on the current temperature inside the computing device. This load schedule ensures that a maximum temperature for the heat sink is not exceeded even when the total system power load exceeds, for a short period of time, the maximum sustainable power level the heat sink can dissipate. The controller may then load the electronic components according to the generated load schedule. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for reduced computing device power consumption. Example methods disclosed herein includes detecting frame updates corresponding to input frames to be presented by a display, causing a programmable timer to generate second interrupts corresponding to first interrupts generated by a display engine, the second interrupts to be generated when there are no frame updates detected for at least a first duration of time defined by a first threshold. Example methods further include causing the display engine to transition to a low power state when (1) the programmable timer is configured to generate the second interrupts and (2) no frame updates have been detected for at least a second duration of time following the first duration of time, the second duration of time defined by a second threshold.

Abstract: The semiconductor device includes a plurality of cores, a sensor for detecting a temperature, and a control circuit configured to obtain each power consumption of the respective cores so as to select the core as a control object in accordance with the obtained power consumption.

Abstract: A sensor system including a detection unit, which is designed to detect at least one physical variable and to output corresponding measured values, and a communication interface, which includes a communication unit and is designed to output the detected measured values at least in a normal operating mode, and which is designed to receive a data signal, which includes a clock signal, the communication unit being designed to use the clock signal as the operating clock in an energy-saving operating mode. Furthermore, a corresponding method is described.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.