Abstract: A computer-implemented method enables rack-level predictive power capping and power budget allocation to processing nodes in a rack-based IHS. A rack-level management controller receives node-level power-usage data and settings from several block controllers, including current power consumption and an initial power budget for each node. A power consumption profile is generated based on the power-usage data for each node. A total available system power of the IHS is identified. A system power cap is determined based on the power consumption profiles and the total available system power. A current power budget is determined for each node based on an analysis of at least one of the power consumption profile, the initial power budget, the current power consumption, the system power cap, and the total available system power. A power subsystem regulates power budgeted and supplied to each node based on the power consumption profiles and the system power cap.

Abstract: System and a method wherein a wearable device receives sensor data at a wearable device and compares a first value determined from the sensor data with a second value determined from the sensor data to determine a percentage change in the sensor data from the first sample to the second sample. The system and method may also change a sampling frequency of the sensor at the wearable device according to one or more settings that were set by a user of the wearable device. The system and method optimizes power consumption while optimally recording data sensed by one or more sensors at a wearable device.

Abstract: Power management contracts for accessory devices are described. In one or more implementations, a power management contract is established for a system including a host computing device and an accessory device based at least in part upon power exchange conditions observed for the system. The power management contracts define operating constraints for power exchange between components of the system, including at least a power exchange direction and current limits. The host computing device and accessory devices are each configured to renegotiate the power management contract to dynamically change operating constraints in “real-time.” Additionally, different power management contracts may be associated with identifying data corresponding to different types of accessory devices.

Abstract: Techniques to inspect packets to determine a destination node are provided. In one aspect, a Wake on Lan (WOL) packet may be received at a switch. A destination node of the WOL packet may be determined. An indication of the determined destination node may be sent to a management controller. The management controller may cause the destination node to awaken.

Abstract: In an information processing apparatus including a plurality of boards, it is possible to appropriately perform initialization of hardware of each board in accordance with a return factor. An information processing apparatus including a first system and a second system, the first system transmitting a boot program of the second system to the second system, and the first system: receives a return factor that causes the information processing apparatus to return from a power-saving state; and is capable of transmitting a first boot program including information indicating a first return factor and a second boot program including information indicating a second return factor to the second system, and the second system: is capable of receiving the first boot program and the second boot program; and performs first boot processing in accordance with the received first boot program and performs second boot processing in accordance with the received second boot program.

Abstract: An information processing apparatus configured to control a parallel computer system, the information processing apparatus includes a processor configured to determine a plurality of power supply control domains by dividing a plurality of computation nodes, acquire scheduling information that indicates an allocation state of one or more first jobs to the plurality of computation nodes, for each of the plurality of power supply control domains, identify, based on the scheduling information, a first number of the computation nodes each of which does not execute the one or more first jobs, receive a request to execute a second job, identify a second number of computation nodes each of which is to be used for processing of the second job, and control to turn on power supply to a first power supply control domain of the plurality of power supply control domains based on the first and second numbers.

Abstract: An electronic system includes a memory controller and a memory. The memory controller generates a plurality of controller clocks having different phases from one another based on a reference clock signal. The memory generates a plurality of internal clocks having different phases from one another by receiving first and second clocks having a phase difference from each other, and outputs one of odd-ordered data and even-ordered data in synchronization with the plurality of internal clocks.

Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

Abstract: A storage control program for causing a computer to perform a process comprising; determining a second number indicating a number of first storage devices in each of which a connection with a controller is established among the two or more first storage devices; and performing control such that a second storage devices, in each of which a connection with the controller is not established among the two or more first storage devices, are caused to transition to a power saving state in a time period in which the second number reaches a first number indicating a number of communication routes used when the controller accesses the two or more first storage devices.

Abstract: A method may include obtaining a concurrent application including processes, each including operations, and obtaining an initial hybrid timestamp for an initial operation of a process. The initial hybrid timestamp may include a vector list timestamp including vector clocks, each including a clock value for each of the processes. The method may further include determining a synchronization category for a next operation of the process, and in response to the synchronization category indicating that the next operation does not require inter-process synchronization, generating a next hybrid timestamp for the next operation. The next hybrid timestamp may include a differential timestamp relative to the initial hybrid timestamp.

Abstract: A memory card reading method applied to an electronic device, includes: detecting a specification information of a memory card, wherein the specification information includes a transfer speed of the memory; and controlling according to the specification information a reader to host interface to operate in a first operating mode or a second operating mode for reading the memory card, wherein the first operating mode and the second operating mode correspond to different data transfer speeds.

Abstract: Disclosed are various embodiments securing the execution of unauthorized applications on a computing device. A file system stored in a storage device includes files and file system data structures. The file system data structures have kernel space accessible portions. When a file is executed, a computing device can determine whether the file can be executed based on a file system data structure corresponding to the file based on the kernel space accessible portion. The operating system can determine whether to execute the file or take another action based on flags stored in the kernel space accessible portion.

Abstract: A method of providing a service of a remote desktop by a main server to a client includes: commanding, before receiving a service request for the remote desktop from the client, the remote desktop to power on; determining, in response to receiving the service request from the client, an operating system corresponding to the client based on the received service request; and supporting booting of the determined operating system of the remote desktop by communicating with the remote desktop.

Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Abstract: An information processing apparatus includes a first processor, a second processor and a positioning processor. The second processor consumes a reduced amount of power compared to the first processor during an operation. The positioning processor receives radio waves from positioning satellites and converts the radio waves into positioning data. The second processor controls the positioning processor. The second processor stores the positioning data received from the positioning processor. The second processor transfers the stored positioning data to the first processor at a timing determined in accordance with an operating condition of the first processor.

Abstract: An information processing apparatus that can communicate with another information processing apparatus is provided.

Abstract: Examples disclosed herein relate to selecting and loading firmware volumes. A computing device is booted to a state where the computing device is capable of accessing a memory available to multiple other computing devices. The memory includes multiple firmware volumes. In one example, at least one firmware volume is selected based on a hardware configuration or hardware components of the computing device. The selected firmware volumes are loaded.

Abstract: An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.