Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
Abstract: A change procedure generating device 10 includes: a storage means 11 which stores, for each relation among constituent elements of a system, a plurality of instances of inter-state information which indicates relations among states of the constituent elements wherein a follow-up state limitation is included which represents a relation between a state transition of the constituent elements of the system and prescribed states to which the constituent elements transition after the state transition has been executed, and an appending means 12 which appends the relations among the states of the constituent elements to an inputted system configuration definition, using the inter-state information which corresponds to the relations among the constituent elements which are included in the configuration definition.
Abstract: Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.
Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.
Type:
Grant
Filed:
May 20, 2019
Date of Patent:
April 6, 2021
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
Inventors:
Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
Abstract: Embodiments of the present disclosure provide a method and apparatus of controlling a network node. The method comprises: providing a virtual PDU by using a computing device; and causing the virtual PDU to control power supply of the network node coupled to the virtual PDU according to a type of the network node. By means of the embodiments of the present disclosure, not only physical nodes can be controlled, but also virtual nodes can be controlled.
Type:
Grant
Filed:
June 17, 2019
Date of Patent:
April 6, 2021
Assignee:
EMC IP Holding Company, LLC
Inventors:
Robert Guowu Xia, Chao Wu, Bryan Xiaoguang Fu, Sophia Xiaoxia Shu, Simon Xingwang Cai, Li Zhai
Abstract: A holster is provided to receive a radio (mobile communications device). The radio is operatively equipped with a front-facing touchscreen. The holster is equipped with an optical reflector. The optical reflector is adapted to change the direction of light rays passing through it in order to reflect only a portion of the front-facing touchscreen to a top window located within the holster. The top window and the touchscreen are substantially perpendicular to each other. The holster is equipped with at least one capacitive touch extension element that couples the top window to a point on the touchscreen to control an interface element on the touchscreen.
Type:
Grant
Filed:
April 22, 2019
Date of Patent:
March 30, 2021
Assignee:
MOTOROLA SOLUTIONS, INC.
Inventors:
Wai Mun Lee, Wooi Ping Teoh, Chun Wen Ooi
Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
Abstract: Techniques are described for improving the boot performance of an operating system (OS) used to launch a virtual machine. In embodiments, a request is received that identifies an OS image and that includes information indicative of when a boot-up process of the OS is complete. A boot-up process of the OS is then performed until complete, as indicated by the information, which includes loading a portion of the OS image from a virtual hard drive. During performance of the process, data is obtained that identifies logical units in the virtual hard drive that are accessed to obtain the portion of the OS image. A copy of the virtual hard drive that include the OS image and the data is then stored so that it can be used to facilitate launching a virtual machine through selective pre-fetching of only the identified logical units from the copy of the virtual hard drive.
Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.
Type:
Grant
Filed:
March 11, 2019
Date of Patent:
March 23, 2021
Assignee:
Intel Corporation
Inventors:
Michael Zelikson, Vjekoslav Svilan, Norbert Unger, Shai Rotem
Abstract: Systems, apparatuses and methods may provide for technology that determines an efficient temperature of a processor based on real-time data and one or more part-specific parameters associated with the processor, determines a set of power differences between other temperatures and the efficient temperature, and stores the set of power differences to a register. In one example, a cooling subsystem is controlled based on the set of power differences in the register.
Abstract: A system for secure load of binary code, comprising a processor, a data memory device configured to be accessible by the processor, a data capsule configured to be accessible by the processor, the data capsule including a data signature and a network interface device configured to authenticate the data signature over a network using a remote data signature verification server.
Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
Type:
Grant
Filed:
December 31, 2019
Date of Patent:
March 9, 2021
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
Inventors:
Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
Abstract: An acquisition unit receives a result of user's selection of an exercise. A time-available-for-operation calculation unit calculates a time available for operation for which an operation on an amount of remaining power of a secondary battery is possibly continued. The determination unit compares a measurement prediction time for which the selected exercise is measured and the time available for operation. When it is determined that the measurement prediction time is longer than the time available for operation, the notification unit notifies a user before the exercise is started.
Abstract: In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.
Type:
Grant
Filed:
March 29, 2019
Date of Patent:
March 2, 2021
Assignee:
Intel Corporation
Inventors:
Ben Furman, Yoni Aizik, Robert P. Adler, Robert Hesse, Chen Ranel
Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.
Type:
Grant
Filed:
December 21, 2015
Date of Patent:
March 2, 2021
Assignee:
Hewlett Packard Enterprise Development LP
Inventors:
Reza Bacchus, Melvin Benedict, Eric L Pope
Abstract: An apparatus in one embodiment comprises at least one processing device having a processor coupled to a memory. The processing device is configured to identify a given computing device that includes two or more storage devices, and to select a given one of the two or more storage devices as a boot disk for the given computing device, the given storage device being in a raw state. The processing device is also configured to write a marker to a designated region of the given storage device in the raw state, and to reboot the given computing device. The processing device is further configured to utilize the marker to identify the given storage device in the raw state as the boot disk for the given computing device subsequent to rebooting the given computing device.
Abstract: A centralized flash memory module is provided. The centralized flash memory module includes flash memory components, a flash memory management controller (FMMC), and a complex programmable logic device (CPLD). Each of the flash memory components is connected to a server device separate from the centralized flash memory module. The FMMC is configured to connect to the flash memory components and to a rack management device, separate from the centralized flash memory module. The CPLD is configured to connect the FMMC to the flash memory components and connect the server device to the flash memory components.
Type:
Grant
Filed:
March 13, 2019
Date of Patent:
February 16, 2021
Assignee:
QUANTA COMPUTER INC.
Inventors:
Ming-Hung Hung, Hsin-Hung Kuo, Chin-Fu Ou
Abstract: A System-on-a-Chip includes a plurality of processing systems and channel circuitry servicing the plurality of processing systems. The channel circuitry includes a clock sprinkler circuit, a clock source, first direction data path circuitry and second direction data path circuitry. A clock sprinkler is a clock signal that propagates in a first direction only, from a source to all destinations. The first direction data path circuitry includes a plurality of first direction data flip flops and first direction combinational logic that service data flow in the first direction. The second direction data path circuitry includes a plurality of second direction data flip flops and second direction combinational logic that service data flow in the second direction.
Abstract: The present disclosure provides a control system and a control method for a double data rate synchronous dynamic random access memory (DDR) system in order to reduce power consumption of the DDR system. The system includes a memory and a processor coupled to the memory, and the processor is configured to monitor a working status of each functional system that shares a power domain with the DDR system, determine a target power parameter value and a target clock parameter value of the DDR system according to the working status of each functional system, and control a power parameter and a clock parameter of the DDR system according to the target power parameter value and the target clock parameter value of the DDR system.