Abstract: An information handling system includes a flash memory and a processor. The processor executes boot instructions including a boot log agent configured to collect initialization phase messages. The flash memory device also includes a circular buffer configured to store the collected initialization phase messages.
Abstract: A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.
Abstract: According to examples, an apparatus may include a power circuit to transmit standby power to a device, a memory associated with the device to maintain first configuration data and second configuration data and a battery to provide backup power to the device. The device may, following a loss and a recovery of the standby power to the device, determine whether the backup power was lost during the loss of the standby power. The device may also, based on a determination that the backup power was lost during the loss of the standby power, read the first configuration data or may, based on a determination that the backup power was not lost during the loss of the standby power, read the second configuration data. The device may further apply the read one of the first configuration data or the second configuration data to configure the device.
Type:
Grant
Filed:
October 10, 2018
Date of Patent:
August 18, 2020
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: Techniques for varying application strategy for different device states are disclosed. In some embodiments, an application strategy for an application running on a mobile device is selected based on a state of the mobile device and executed with respect to the application while the mobile device remains in that state. A different application strategy is selected and executed with respect to the application when the mobile device enters a different state. That is, different application strategies are selected and executed with respect to the application for different detected states of the mobile device.
Type:
Grant
Filed:
March 30, 2018
Date of Patent:
August 18, 2020
Assignee:
shopkick, Inc.
Inventors:
Joseph Reginald Scott Molnar, Todd Sean Murchison
Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.
Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.
Abstract: Methods and systems are disclosed which may consolidate a flash management entity using IO virtualization. The consolidation may occur in a centralized location. Furthermore, a boot strap may be created to allow booting of the micro server from a virtualized firmware management entity.
Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.
Type:
Grant
Filed:
January 18, 2019
Date of Patent:
July 14, 2020
Assignee:
Intel Corporation
Inventors:
Surya Musunuri, Jagannadha R. Rapeta, Mark L. Elzinga, Young Min Park, Robert R. Fulton
Abstract: Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.
Type:
Grant
Filed:
February 28, 2018
Date of Patent:
July 14, 2020
Assignees:
Advanced Micro Devices, Inc., ATI Technologies ULC
Inventors:
Benjamin Tsien, Alexander J. Branover, Ming L. So, Philip Ng, Xiao Gang Zheng, Felix Ho, Joseph Scanlon, Christopher T. Weaver, Xiaojie He, Carl Kittredge Wakeland
Abstract: An electronic device includes a display and a processor. The processor controls the display to operate in a full display mode to display a full color user interface, detects whether a first predetermined trigger event occurs, controls the display, when the first predetermined trigger event occurs, to switch from the full display mode to a partial display mode, generates a partial interface and displays the partial interface on the display, and switches from an operating mode to a sleep mode after the partial interface is displayed on the display.
Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.
Type:
Grant
Filed:
May 21, 2018
Date of Patent:
June 30, 2020
Assignee:
BAE Systems Information and Electronic Systems Integration Inc.
Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.
Abstract: The present invention relates to a control system, in particular a lighting control system, having a control line to control power modes of network components, such as data forwarding components as well as end nodes, e.g. application control components, according to a global application plan. Controlling the power modes may comprise switching off data-ports in the control network. A data-forwarding device having switchable data port can be used to switch off data paths “in efficio” through the control network. Furthermore, a protocol to interrogate the status of a network component as well as to receive a schedule for unattended operation is provided, thereby enabling improved energy usage and enhanced safety.
Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.
Abstract: A power adapter device may use a method for efficient charging of multiple portable information handling systems based on learned charging characteristics. In particular, when electrical power is delivered to at least one of the portable information handling systems, the power adapter device may prioritize electrical power delivery to another portable information handling system ahead of the portable information handling systems based on the learned charging characteristics such that charging is efficient.
Type:
Grant
Filed:
September 1, 2017
Date of Patent:
June 2, 2020
Assignee:
Dell Products L.P.
Inventors:
Karthikeyan Krishnakumar, Richard Christopher Thompson
Abstract: A method for identifying a hardware device in an operating system and a computer apparatus are provided. The method includes determining a unique index identifier of a hardware device, and establishing a mapping relationship between the unique index identifier and a device number of the hardware device. The method also includes obtaining the unique index identifier of the hardware device, in response to a status change of a hardware interface. Further, the method includes according to the mapping relationship, obtaining and allocating the device number to the hardware device to enable an access to the hardware device according to the device number of the hardware device.
Abstract: A method utilizes event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in a logically-partitioned computing environment in response to detection of a system event that is likely to increase or decrease the collective resource demands of logical partitions resident in a logically-partitioned computing environment. The reoptimization may be used to consolidate logical partitions on fewer processor nodes to improve the potential for powering down hardware resources and thereby reduce power consumption.
Type:
Grant
Filed:
November 27, 2017
Date of Patent:
May 26, 2020
Assignee:
International Business Machines Corporation
Inventors:
Curtis S. Eide, Aditya Kumar, Kevin Wendzel
Abstract: The present invention is applicable to the field of hard disk processing technologies, and provides a hard disk system operation method, a storage system, and a processor. The method includes: starting, by a processor, a Boot Loader recorded in a non-volatile storage medium, configuring an IP address for the storage system after the loader is started, and then establishing, based on the IP address, an IP transmission channel between an external interface and a server; obtaining, by the processor, hard disk firmware from the external interface, where the hard disk firmware is received by the external interface from the server through the IP transmission channel; and suspending, by the processor, a hard disk, and loading the hard disk firmware to a memory.
Abstract: An Ethernet power sourcing equipment (PSE), and a method and an apparatus for power over Ethernet (PoE), where the Ethernet PSE includes a PSE chip, a master control processor, a power supplying port, and a preprocessor. The preprocessor is configured to determine whether the master control processor starts upon power-on, control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on, and control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD. Hence, the Ethernet PSE has abundant management functions and can quickly power on a PD.
Abstract: A computer-implemented method enables rack-level predictive power capping and power budget allocation to processing nodes in a rack-based IHS. A rack-level management controller receives node-level power-usage data and settings from several block controllers, including current power consumption and an initial power budget for each node. A power consumption profile is generated based on the power-usage data for each node. A total available system power of the IHS is identified. A system power cap is determined based on the power consumption profiles and the total available system power. A current power budget is determined for each node based on an analysis of at least one of the power consumption profile, the initial power budget, the current power consumption, the system power cap, and the total available system power. A power subsystem regulates power budgeted and supplied to each node based on the power consumption profiles and the system power cap.
Type:
Grant
Filed:
August 3, 2017
Date of Patent:
May 19, 2020
Assignee:
Dell Products, L.P.
Inventors:
Edmond Bailey, John Stuewe, Paul Vancil, Kunrong Wang, German Florez-Larrahondo