Abstract: The present disclosure is directed to controlled customization of silicon initialization. A device may comprise, for example, a boot module including a memory on which boot code is stored, the boot code including at least an initial boot block (IBB) module that is not customizable and a global platform database (GPD) module including customizable data. The IBB module may include a pointer indicating GPD module location. The customizable data may comprise configurable parameters and simple configuration language (SCL) to cause the device to execute at least one logical operation during execution of the boot code. The GPD module may further comprise a pointer indicating SCL location. The boot code may be executed upon activation of the device, which may cause the IBB module to load an interpreter for executing the SCL. The interpreter may also verify access request operations in the SCL are valid before executing the access request operations.

Abstract: Methods, apparatus, systems and articles of manufacture to optimize power consumption and capacity in a multi-mode communication system are disclosed. A utilization factor controller is to estimate power consumption values corresponding to a plurality of first utilization factor and second utilization factor pairs, the first utilization factor corresponding to utilization of the first transceiver that is to communicate using a first protocol, the second utilization factor corresponding to utilization of the second transceiver that is to communicate using a second protocol different form the first protocol, the utilization factor controller to select a first utilization factor and second utilization factor pair based on the estimated power consumption value. A transmission time controller is to calculate first and second transmission times to be used by the first and second transceiver based on the selected first utilization factor and second utilization factor pair.

Abstract: A device is provide including: a storage device comprising a memory configured to store configuration data used for test booting for a process of testing the device, before the test booting; and a controller configured to perform the test booting using the stored configuration data when receiving a start signal of the test booting, to control the process of testing the device to be performed after the test booting, and to delete the configuration data stored in the storage device when a completion signal of the process of testing the device is received.

Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

Abstract: Techniques are described for improving the boot performance of an operating system (OS) used to launch a virtual machine. In embodiments, a request is received that identifies an OS image and that includes information indicative of when a boot-up process of the OS is complete. A boot-up process of the OS is then performed until complete, as indicated by the information, which includes loading a portion of the OS image from a virtual hard drive. During performance of the process, data is obtained that identifies logical units in the virtual hard drive that are accessed to obtain the portion of the OS image. A copy of the virtual hard drive that include the OS image and the data is then stored so that it can be used to facilitate launching a virtual machine through selective pre-fetching of only the identified logical units from the copy of the virtual hard drive.

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

Abstract: A power coupling device with detection and power adjustment function includes at least one detection unit, at least one switch unit, at least one coupling unit, at least one amplification unit, at least one comparison unit and at least one logic unit. The detection unit serves to receive a first operation power and a second operation power. The coupling unit serves to couple the first and second operation powers for a power output end to output a regulated output power. The comparison unit serves to compare to generate a first comparison result and a second comparison result. According to the first and second comparison results, the logic unit logically judges to generate a triggering signal for controlling the switch unit to turn on or turn off the switch unit so as to adjust the power of the regulated output power.

Abstract: An integrated circuit (IC) is disclosed herein for power management using duty cycles. In an example aspect, the integrated circuit includes multiple power domains, each of which includes a respective power state controller. The power state controller acts as a bridge between global supply lines of the integrated circuit and local supply lines of the respective power domain. Global supply lines can include a first global power rail, a second global power rail, and a global clock tree. Local supply lines can include a local power rail and a local clock tree. In operation, a power state controller adjusts a power state of the respective power domain in accordance with a duty cycle. A timeslot corresponding to the duty cycle can be separated into multiple time periods with durations of the time periods being based on the duty cycle.

Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.

Abstract: Devices include a processor and a memory. The processor is configured to determine if a bootloader area does not contain a valid bootloader instruction set, to locate a bootloader instruction set, and to copy the bootloader instruction set to the bootloader area. The processor then executes the bootloader instruction set from the bootloader area.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: An electronic apparatus operates in a normal mode and a power-saving mode. A smaller amount of electricity is consumed in the power-saving mode than in the normal mode. The electronic apparatus includes a control section and a connection interface to which a reader that reads information from an external storage medium is connectable. When the electronic apparatus transits from the normal mode to the power-saving mode, if the reader is connected to the connection interface, the control section transits to a first power-saving mode in which both the connection interface and the reader are operable, or if the reader is not connected to the connection interface, the control section transits to a second power-saving mode in which a lower amount of electricity is consumed than in the first power-saving mode.

Abstract: An information handling system includes a battery, a host processing complex, and a management system. The battery includes a battery power level gauge that determines a power level of the battery. The management system includes a wireless transceiver. When the host processing complex is unpowered, the management system is coupled to receive power from the battery and provides a first indication of the power level of the battery via the wireless transceiver.

Abstract: A secure boot computer system is provided. The system comprises a logic block comprising one or more processing units that executes instructions, the logic block being configured to request boot instructions over a first interface, according to a first communication protocol, on power-up or reset of the logic block. A controller component is configured to communicate with the logic block over the first interface according to the first communication protocol, the controller being further configured to implement a communications link to a second computer system and to receive the boot instructions from the second computer system. The logic block is preconfigured to communicate with the controller over the first interface according to the first communication protocol in a manner that cannot be altered by instructions executed by the logic block. The controller is configured to prevent the completion of any write requests from the logic block.

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

Abstract: Example implementations relate to booting a system comprising a system-on-a-chip (SOC) device. For example, boot code and system code comprising at least one selected from among an operating system and hypervisor code are stored in an on-chip non-volatile memory of a SoC device. By executing the boot code from the on-chip non-volatile memory, the system is booted from a mode in which power is removed from the system, where the booting includes loading the system code in the SoC device from the on-chip non-volatile memory without accessing storage off the SoC device.

Abstract: A computer system for hosting a virtual power system environment includes a plurality of virtual devices, wherein at least one of the plurality of virtual devices is configured to simulate the function of at least one physical device in a power system, a virtual device manager configured to perform at least one operation on the plurality of virtual devices, a virtual power monitor configured to control a function of the plurality of virtual devices, a simulation engine configured to simulate a performance of the plurality of virtual devices according to conditions detected on the power system, and a configuration generator configured to generate a configuration for a physical power monitor according to a configuration of the virtual power monitor.

Abstract: A computer processing system includes a processor to operate based on an operating system providing an operating system user interface, and to detect when a user session is opened. A memory is coupled to the processor and is configured to store the operating system. A thin client conversion engine is configured to perform, in response to the opened user session and before the user can interact with the operating system setting at least one hook to manage control of user interactions with the operating system, and intercepting at least one shell component of the operating system so that the at least one shell component is not available to the user. State information on the at least one shell component at the time of intercept is saved in the memory. The thin client conversion engine redefines the operating system user interface based on the setting and intercepting without making any changes to the operating system.

Abstract: As part of starting a system including a system-on-a-chip (SoC) device from a mode in which power is removed from the system, the SoC device determines, based on the metadata, whether to resume the system to a prior system state. In response to the metadata indicating that the system is to be resumed to the prior system state, the system is resumed to the prior system state using system state information stored in the on-chip non-volatile memory.

Abstract: A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.