Abstract: Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.

Abstract: Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage.

Abstract: A hard disk drive includes a base, a disk to record and store data, a head stack assembly provided in the base to read out data from the disk which rotates about a pivot shaft, and an air force dispersion unit positioned adjacent to the head stack assembly to disperse an air force generated during a rotation of the disk.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The distribution state of the threshold voltages of the memory cells is monitored by the read operation, the distribution state of the threshold voltages of the memory cells after the soft erasure is monitored, and an erase voltage is set based on the monitored results. Thus, the erase voltage can be precisely set without depending on the threshold voltage distribution of the memory cell before the erasure.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array and a controller. The memory cell array includes first, second, and third memory cells each of which stores k-bit data (where k is a natural number not smaller than 1). The first and second memory cells are adjacent to each other, and the second and third memory cells are adjacent to each other. Data is stored into the memory cells in an order of the first, second, and third memory cells. When reading data from the second memory cells, the controller reads data from the first and third memory cells, and changes read conditions for the second memory cell in accordance with the read data.

Abstract: A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

Abstract: A memory circuit comprising a set of longitudinal conducting lines and a set of transverse conducting lines, wherein, each conducting line comprises alternating regions of reduced and increased line widths. The set of transverse conducting lines overlies the set of longitudinal conducting lines to define crossover zones wherein the reduced line width regions of the transverse conducting lines cross over the reduced line width regions of the longitudinal conducting lines. The circuit further comprises addressable magnetic storage elements, each disposed within a crossover zone between a longitudinal conducting line and a transverse conducting line thereof. The reduced line width regions improve magnetic flux efficiency in the magnetic storage elements and the increased line width regions lower the resistance in the conducting lines.

Abstract: Micromagnetic elements, logic devices and methods of fabricating and using them to store data and perform logic operations are disclosed. Micromagnetic elements for data storage, as well as those providing output from a logic device, are at least partially covered with an optical coating that facilitates determination of the magnetic state. The disclosed logic devices perform one or more of AND, OR, NAND and NOR operations.

Abstract: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential.

Abstract: A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.

Abstract: A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N?1)th page programming operation and before the Nth page programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells.

Abstract: A nonvolatile semiconductor storage device according to an embodiment includes a write/erase unit, during data write or erase, the write/erase unit supplying a first electric pulse to a selected memory cell, the first electric pulse having an electric energy to an extent that an physical state of a memory element of the selected memory cell does not transition and accumulating charges in a rectifying element of the selected memory cell, after supplying the first electric pulse, and a certain pulse interval thereafter, and supplying a second electric pulse to the selected memory cell, the second electric pulse having larger electric energy than the first electric pulse, the second electric pulse causing the physical state of the memory element of the selected memory cell to transition.

Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).

Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.

Abstract: Disclosed are a semiconductor device capable of testing memory cells and a test method. The semiconductor device includes a plurality of terminals, each terminal being configured to receive similar data during a test mode, a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal, and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer.

Abstract: This application discloses a Load-UnLoad (LUL) hard disk drive comprising a disk base, a spindle motor mounted on the disk base for rotating at least one disk to create at least one rotating disk surface, and a head stack assembly pivotably coupled to the disk base and configured to engage an actuator latch when the sliders of the head stack assembly are to be parked. The actuator latch includes a latch beam coupled through a latch pivot to the disk base and a boss coupled to the latch beam and configured to limit the stroke of latch motion in the event of a rotary non-operational shock.

Abstract: A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.

Abstract: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.

Abstract: A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.

Abstract: The control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing: (i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device; (ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and (iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data.