Patents Examined by Pablo Huerta
  • Realignment of command slots after clock stop exit
    Patent number: 8787110
    Abstract: Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: Tuan M. Quach, Victor V. Tran
  • Pinning magnetic domain walls in a magnetic domain shift register memory device
    Patent number: 8787062
    Abstract: A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Semiconductor memory device
    Patent number: 8780614
    Abstract: The capacitance of a capacitor that is required in a DRAM is reduced, whereby a highly integrated DRAM is provided. In a divided bit line type DRAM, a sub bit line is formed below a word line and a bit line is formed above the word line. The parasitic capacitance of the sub bit line is reduced by employing the divided bit line method, and further, the off resistance of a cell transistor is set high according to need; thus, the capacitance can be one tenth or less of that of a conventional DRAM. Accordingly, even when a stacked capacitor is employed, the height of the capacitor can be one tenth or less of that of a conventional one, so that a bit line can be easily provided thereover. Further, by devising a structure of the cell transistor, the area per memory cell can be reduced to 4 F2.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Integrated circuit including a voltage divider and methods of operating the same
    Patent number: 8780628
    Abstract: An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yvonne Lin, Wen-Ting Chu
  • Programming to mitigate memory cell performance differences
    Patent number: 8773910
    Abstract: Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mason Jones
  • Semiconductor memory device and method of writing into semiconductor memory device
    Patent number: 8773918
    Abstract: The semiconductor memory device includes a memory cell, a pair of bit lines and a cell power line connected to the memory cell, a first switch connected to the bit lines and a power voltage line, a second switch connected to the cell power line and a write assist cell power line, and a write control circuit configured to control the bit lines, the first switch and the second switch, wherein the write control circuit applies a first voltage of a high level to one bit line and a second voltage of a low level to the other bit line, connects one bit line to the power voltage line and disconnects the other bit line from the power voltage line by the first switch, and then connects the cell power line to the write assist cell power line lower which is than the first voltage by the second switch.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryo Tanabe
  • Fluid dynamic bearing unit and disk drive device including the same
    Patent number: 8760810
    Abstract: A first sleeve rotatably extends around a shaft. First and second flanges are fixed to the shaft. A second sleeve extending around the first sleeve is fixed thereto. A first annular member fixed to the second sleeve surrounds the first flange. A second annular member fixed to the second flange surrounds a portion of the second sleeve. A first capillary seal includes a clearance between the first flange and the first annular member. A second capillary seal includes a clearance between the second annular member and the second sleeve. Lubricant is provided in the clearances in the first and second capillary seals. The second annular member and the second sleeve are designed so that the lubricant in the clearance in the second capillary seal can be viewed from a point in a radial position which is outward of the second sleeve as seen in an axial direction.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.
    Inventor: Ryusuke Sugiki
  • Non-volatile memory (NVM) that uses soft programming
    Patent number: 8760923
    Abstract: A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: June 24, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fuchen Mu, Yanzhuo Wang
  • High voltage generating circuit and method of operating the same
    Patent number: 8755242
    Abstract: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first delay circuit configured to output the second clock signal by delaying the first clock signal by a first delay time. The first delay circuit is configured to adjust the first delay time according to a period of the first clock signal.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheon An Lee, Doogon Kim
  • Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)
    Patent number: 8755221
    Abstract: A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 17, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Petro Estakhri, Ebrahim Abedifard, Frederick Jaffin, Siamack Nemazie
  • Semiconductor memory device
    Patent number: 8750023
    Abstract: An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuma Furutani, Yutaka Shionoiri
  • Semiconductor recording device
    Patent number: 8750032
    Abstract: The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Kawahara, Riichiro Takemura, Takashi Ishigaki, Kiyoo Itoh
  • Semiconductor memory apparatus
    Patent number: 8750064
    Abstract: A semiconductor memory apparatus includes a first switch, a second switch and a control unit. The first switch couples/separates a first bit line and a sense amplifier to/from each other in response to a first bit line separation signal. The second switch couples a second bit line and the sense amplifier to each other in response to a second bit line separation signal. The control unit generates a bit line separation signal for a refresh operation, of which enable period is shorter than that of the second bit line separation signal, and provides the generated bit line separation signal for the refresh operation to the second switch in the refresh operation.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventor: So Jeong Kim
  • Internal voltage generation circuit of semiconductor memory device, and semiconductor memory device
    Patent number: 8737142
    Abstract: An internal voltage generation circuit includes a vblh voltage generation circuit that generates a voltage vblh that is supplied as a high-voltage power supply of a sense amplifier, and a voltage distribution control circuit that has a first current source that pulls down an output node and a second current source that pulls up the output node. The output node is pulled down by the first current source operating, and the voltage thereof is maintained at a voltage that corresponds to a lower limit of a detection voltage value. The output node is pulled up by the second current source operating, and the voltage thereof is maintained at a voltage that corresponds to an upper limit of the detection voltage value.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiko Sato
  • Method of programming a semiconductor memory device
    Patent number: 8730735
    Abstract: A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word line.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Je Park
  • Memory apparatus and system with shared wordline decoder
    Patent number: 8730754
    Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gerald Barkley, Efrem Bolandrina, Daniele Vimercati
  • Graphene-based non-volatile memory
    Patent number: 8724402
    Abstract: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventor: Wenjuan Zhu
  • Semiconductor memory device
    Patent number: 8717836
    Abstract: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventor: Takeo Yasuda
  • Reconfigurable multi-level sensing scheme for semiconductor memories
    Patent number: 8717802
    Abstract: A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Scott C. Lewis, Jing Li
  • Nonvolatile memory device
    Patent number: 8711609
    Abstract: A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 29, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung Yeon Lee