Abstract: A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality.

Abstract: A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

Abstract: A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.

Abstract: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.

Abstract: A first sleeve rotatably extends around a shaft. First and second flanges are fixed to the shaft. A second sleeve extending around the first sleeve is fixed thereto. A first annular member fixed to the second sleeve surrounds the first flange. A second annular member fixed to the second flange surrounds a portion of the second sleeve. A first capillary seal includes a clearance between the first flange and the first annular member. A second capillary seal includes a clearance between the second annular member and the second sleeve. Lubricant is provided in the clearances in the first and second capillary seals. The second annular member and the second sleeve are designed so that the lubricant in the clearance in the second capillary seal can be viewed from a point in a radial position which is outward of the second sleeve as seen in an axial direction.

Abstract: Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to assure proper operation of the functional circuit while operating with performance, voltage, temperature (PVT) delay variations. In this regard, a performance monitoring circuit is provided in the semiconductor die that includes the functional circuit. As a result, the performance monitoring circuit may be exposed to similar delay variations as the functional circuit. The performance monitoring circuit is configured to measure a performance characteristic(s) associated with the semiconductor die.

Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

Abstract: Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Abstract: A first sleeve rotatably extends around a shaft. First and second flanges are fixed to the shaft. A second sleeve extending around the first sleeve is fixed thereto. A first annular member fixed to the second sleeve surrounds the first flange. A second annular member fixed to the second flange surrounds a portion of the second sleeve. A first capillary seal includes a clearance between the first flange and the first annular member. A second capillary seal includes a clearance between the second annular member and the second sleeve. Lubricant is provided in the clearances in the first and second capillary seals. The second annular member and the second sleeve are designed so that the lubricant in the clearance in the second capillary seal can be viewed from a point in a radial position which is outward of the second sleeve as seen in an axial direction.

Abstract: A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line.

Abstract: Various embodiments of a semiconductor integrated circuit apparatus are disclosed. In one exemplary embodiment, the apparatus may include a memory cell array having a plurality of memory cell blocks, a plurality of word line selection sections corresponding to the plurality of memory cell blocks, a block selection unit configured to provide a driving signal to the plurality of word line selection sections for driving the plurality of memory cell blocks, and a plurality of global line groups, each corresponding to one of the plurality of word line selection sections. Each of the global line groups may include a plurality of signal lines configured to provide a voltage signal to the corresponding word line selection section.

Abstract: Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.

Abstract: An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor. The memory cell includes a writing transistor, a reading transistor, and a selecting transistor. Using a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and holding data for a long time can be provided.

Abstract: A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.

Abstract: According to one embodiment, a semiconductor storage device includes a memory string, a bit line, a sense simplifier, a first MOS, a first charging-circuit, a second-charging circuit, and a controller. The memory string includes memory cells. The bit line is connected to the memory cell. The sense amplifier applies a voltage to the bit line. The first MOS is electrically connected between the sense amplifier and bit line. The first charging circuit has a first current supply capacity and transfers a first current. The second charging-circuit has a second current supply capacity. The controller controls a first timing to switch from the first current to the second current.

Abstract: A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data transmission line to a first potential at the time of a first write mode in which data masking is not performed. The data transmission line precharge circuit sets the precharge potential to a potential different from the first potential at the time of a second write mode in which data masking is performed. When data masking is not carried out, precharging to a potential at which data can be written in excellent fashion can be performed. When data masking is carried out, precharging to a potential that inhibits a fluctuation in bit-line potential can be performed.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and are capable of storing write data and/or read data for the columns. The latch circuits are selectively activated, and activated latch circuits are capable of receiving and/or outputting data.