Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential.

Abstract: A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line. A write current controller configured to control activation of a write control signal in response to an output of the voltage detector, and a write driver configured to control amounts of write current applied to the memory cell according to the activation of the write control signal.

Abstract: A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.

Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.

Abstract: A first sleeve rotatably extends around a shaft. First and second flanges are fixed to the shaft. A second sleeve extending around the first sleeve is fixed thereto. A first annular member fixed to the second sleeve surrounds the first flange. A second annular member fixed to the second flange surrounds a portion of the second sleeve. A first capillary seal includes a clearance between the first flange and the first annular member. A second capillary seal includes a clearance between the second annular member and the second sleeve. Lubricant is provided in the clearances in the first and second capillary seals. The second annular member and the second sleeve are designed so that the lubricant in the clearance in the second capillary seal can be viewed from a point in a radial position which is outward of the second sleeve as seen in an axial direction.

Abstract: A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ.

Abstract: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.

Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract: Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages applied to an access line coupled to a selected memory cell can be determined at least partially in response to a sensed operating characteristic of the memory device, such as operating temperature, and to a particular data state to be determined in the selected memory cell.

Abstract: Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage. Various embodiments include the array architecture to facilitate precharging the adjacent pair of data lines to a particular voltage and maintaining the unselected data line at the particular voltage during a sensing phase of a read operation.

Abstract: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data.

Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

Abstract: A method of testing bitlines in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bitlines crossing the memory cell array. Each of the bitlines has a first end and a second end. The bitlines are divided into a first group and a second group. The testing method includes applying a supply voltage (for charging) or a ground voltage (for discharging) to a specific group of bitlines. The bitlines are tested in two testing stages, namely an open-circuit bitline test and a short-circuit bitline test, based on the feature that a defective bitline cannot be charged or discharged. The open-circuit bitline test and the short-circuit bitline test are quick and dispense with a lengthy programmed/erasing process.

Abstract: Methods, systems, and apparatus, including computer program products for programming memory. In one aspect, a program circuit includes a first transistive element; a second transistive element coupled to a first end of the first transistive element; a burn subcircuit, the burn subcircuit including a third transistive element coupled to a fourth transistive element, where the drain of the third transistive element is coupled to a second end of the first transistive element, and the source of the third transistive element is coupled to the drain of the fourth transistive element; and a fifth transistive element coupled in parallel to the fourth transistive element. Control logic coupled to the first transistive element, the burn subcircuit, and the fourth transistive element selectively enables the second transistive element, selectively enables the fourth transistive element, and selectively enables the fifth transistive element to enable a read mode or a program mode.

Abstract: A non-volatile memory device for performing a sensing operation using a current signal includes a cell array, a current-voltage converter, and a sense amplifier. The cell array includes at least one unit cell so as to read or write data. The current-voltage converter converts a sensing current corresponding to data stored in the unit cell into a sensing voltage, outputs the sensing voltage, receives a feedback input of the sensing voltage, and adjusts a level of a current applied to an input terminal of the sensing current in response to a level of the feedback input sensing voltage. The sense amplifier compares the sensing voltage with a predetermined reference voltage, and amplifies the result of comparison.

Abstract: A bit line sense amplifier control circuit is configured to drive a bit line sense amplifier according to a first sense amplifier enable signal and a second sense amplifier enable signal, wherein the driving force of the bit line sense amplifier is changed in response to a column selection control signal.