Abstract: A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock.

Abstract: A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that pass testing. Each signal of each die in the memory module has an unique bond-out or connection point in the package of the memory module. By separating the signals of each die in the memory module, any defective die can be easily isolated and this allows a significant cost reduction in products that use a large number of dies.

Abstract: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.

Abstract: This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.

Abstract: Memory cells adjacent to each other in a second direction are formed in a first p-type well region, a first n-type well region, and a second p-type well region arranged in a first direction. Each memory cell includes a first transfer transistor and a first driver transistor formed in the first p-type well region, a second transfer transistor and a second driver transistor formed in the second p-type well region, and first and second load transistors formed in the first n-type well region. In an SRAM, gate electrodes of the first and second transfer transistors of the memory cells adjacent to each other in the second direction are electrically connected to first and second word lines, respectively. The first and second word lines are electrically connected to the first and second p-type well regions, respectively.

Abstract: A semiconductor device includes a plurality of bank sets and an address controller. Each bank set includes a plurality of banks. Each bank includes a plurality of memory mats and sense amplifier arrays corresponding to row addresses. The plurality of bank sets is arranged in both sides of arrays of power electrode pads to be used for operations of the sense amplifier arrays. The plurality of bank sets commonly shares the arrays of power electrode pads. The address controller generates different row addresses that are supplied to different ones of the plurality of bank sets. The different row addresses designate different memory mats in the different ones of the plurality of bank sets, so as to designate different arrays of the power electrode pads for the different ones of the plurality of bank sets for refresh operation in accordance with an external refresh command.

Abstract: A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.

Abstract: A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

Abstract: A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global I/O line pair, the local I/O line pair including a first local I/O line and a second local I/O line, and a local I/O line control unit including a first capacitor and a second capacitor, the first capacitor increasing a voltage level of the first local I/O line based on the local sensing enable signal, the second capacitor increasing a voltage level of the second local I/O line based on the local sensing enable signal.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.

Abstract: An interface circuit having a first signal path and a second signal path is disclosed. The first and second signal paths are coupled between a first and second nodes, wherein the first node is coupled to receive signals from a source external to an integrated circuit upon which the interface circuit is implemented. Each of the first and second signal paths include circuitry implemented with transistors rated at higher voltages than internal circuitry coupled to receive signals therefrom. The first and second signal paths may utilize different circuit topologies. The interface may thus be used in environments where external circuitry coupled to the external input node conforms to one of a number of different standards (e.g., LPDDR1 and LPDDR2).

Abstract: A storage apparatus 10 that writes data to a storage drive 20 or reads data from a storage drive 20 in response to an I/O request sent from a server apparatus 2, and includes a plurality of AC-DC power supplies to supply the storage drive 20 with drive power is provided with a plurality of power supply paths provided for the respective AC-DC power supplies 22 configured to supply the storage drive 20 with drive power from the AC-DC power supplies 22, respectively and a plurality of gate units provided to the respective power supply paths and configured to stop supplying drive power to the storage drive 20 through the corresponding power supply path when detecting voltage abnormality in the drive power supplied from the AC-DC power supply 22 to the storage drive 20. For example, the power supply paths are provided to allow each of the storage drives 20 belonging to a same RAID group 51 to receive the supply of the drive power from the AC-DC power supplies 22 through different power supply paths, respectively.

Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region.

Abstract: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Abstract: A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage with a highest voltage. If a first shift value as a difference between a least frequent voltage of the threshold voltage distribution and the first HB read voltage is “negative”, the memory card performs decoding based on an LLR acquired from the second LLR table. If the first shift value is “positive”, the memory card performs decoding based on an LLR acquired from a third LLR table.

Abstract: Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array including cells provided at each of intersections of first and second lines and each having a variable resistance element and a first diode connected in series; a first line control circuit for supplying voltages to the first lines; and a second line control circuit for supplying voltages to the second lines, the cells each having one of the second lines connected to an anode side of the first diode and one of the first lines connected to a cathode side of the first diode, and the memory cell array including a second diode inserted in each of the second lines between the second line control circuit and the cells and each having a side of the second line control circuit as an anode and a side of the cells as a cathode.

Abstract: Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.

Abstract: On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.

Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.