Abstract: A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier.

Abstract: Embodiments of amplifiers with depletion and enhancement mode thin film transistors are disclosed herein. Other examples, devices, and related methods are also disclosed herein.

Abstract: An amplifier having an imbalance between pull-up and pull-down sections may include a counterpart section to balance the output sections and/or enable them to be driven by balanced drive signals. In one embodiment, a rail-to-rail output stage may include a current minor to drive one side of the circuit. The other side may be driven by a transistor having a counterpart transistor to balance the circuit. A drive section may include a balance point to facilitate balancing the drive signals.

Abstract: Active resistive circuitry (10, 10A, 11, 11A 25, 30, 35, or 40) includes a first current divider circuit (11) having an input (15) coupled to a first signal (Vi). The first current divider circuit (11) includes a first amplifier (13) having a first input (?) coupled to the first signal (Vi). A symmetrically bilateral first bidirectional circuit (M1a,M1b; R1) is coupled between the first input (?) of the first amplifier (13) and an output (17) of the first amplifier (13), and functions as a feedback circuit of the first amplifier (13). A symmetrically bilateral second bidirectional circuit (M2a,M2b; R2) is coupled between the output (17) of the first amplifier (13) and an output (18) of the first current divider circuit (11).

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits embodiments such as operational transconductance amplifiers (1101, 1102, 1103), biasing circuits, integrators (1113, 1123, 1133), continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Driver circuits and methods related thereto for driving high power and/or high frequency devices are described. The driver circuits comprise transistor stacks and capacitors coupled with the transistor stacks. Voltages across the capacitors depend on state (on or off) of each transistor in the transistor stacks. These voltages in turn determine output voltages generated by the driver circuits.

Abstract: A high efficiency linear amplifier is disclosed. The amplifier comprises an input module having an input coupled to receive an input signal, a first output configured to provide a first signal component, and a second output configured to provide a second signal component. The amplifier also comprises a switching module having a switch input coupled to receive a switch signal, a first input coupled to the first output of the input module, a second input coupled to the second output of the input module, and at least a first output configured to provide a first composite signal.

Abstract: A programmable device includes an operational amplifier and circuitry. The operational amplifier is configured to generate an output voltage based on input voltages at input terminals thereof. The circuitry is configured to provide the input voltages to the operational amplifier. The configuration of the circuitry allows the programmable device to implement discrete-time or continuous-time functions. The circuitry includes a resistor network and a capacitor network configured to be selectively coupled to the operational amplifier.

Abstract: An audio amplifier circuit has a first cascode stage configured as a voltage gain stage and having an input for an audio signal, and an output. The circuit has a second cascode stage configured as a unity gain or near unity gain stage and having an input to receive an output from the first cascode stage, and a low impedance output to drive an output stage of an audio power amplifier. The first cascode stage has a first, input transistor having an input biased to a predetermined bias voltage, and a second, output transistor arranged to drive the second cascode stage. The first, input transistor of the first cascode stage may have a common-emitter configuration, and the second, output transistor may have a common-base configuration. The invention extends to an audio amplifier which includes a circuit of the invention.

Abstract: When an output voltage from the amplifying circuit includes a positive DC voltage, an electric current continuously flows in a power source voltage, a load, and a reference voltage in this order. As a result, the reference voltage increases so as to be a first threshold voltage or more . The detecting section detects that the reference voltage is the first threshold voltage or more. When the output voltage from the amplifying circuit includes a negative DC voltage, an electric current continuously flows in the reference voltage, the load, a grounding potential in this order. As a result, the reference voltage reduces so as to be a second threshold voltage or less. The detecting section detects that the reference voltage is the second threshold voltage or less.

Abstract: A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

Abstract: An amplifier circuit and a method of signal amplification are provided. The amplifier circuit includes a first amplifier and a charge pump. The first amplifier includes a first terminal, a second terminal, and a third terminal. The first terminal is coupled to a first external voltage. The second terminal is coupled to a negative voltage. The third terminal is coupled to a ground reference voltage. The charge pump is coupled to the first amplifier for providing the negative voltage transformed from a second external voltage.

Abstract: Several push-pull linear hybrid class H amplifiers are disclosed. A split power rail provides a positive supply rail and a negative supply rail in response to a power supply control voltage. A push-pull amplifier stage is powered by the positive and negative supply rails. The amplifier stage receives an input signal and provides a corresponding amplified output signal. A power supply control circuit provides the power supply control voltage in response to the smaller of the positive and negative supply rails, and the input signal.

Abstract: Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. A decoder receives and decodes the codewords by comparing symbols on node pairs for which the symbols expressed in the prior code word were alike and decoding the results of those comparisons.

Abstract: An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed.

Abstract: An apparatus for detecting bus connection is provided for determining whether an electrical connector of a peripheral device is connected to an electrical connection port. In the apparatus, a detection capacitor is electrically coupled to a detection pin in the electrical connection port, and a controller is provided to transmit a detection signal to the detection pin. According to the signal fed back by the detection capacitor, the occurrences of the charge and discharge phenomena in the detection capacitor are determined, and then the controller is able to determine whether the detection pin of the electrical connector is electrically coupled to the electrical connector, so as to initiate a system event. The detection pin is not electrically charged when the detection pin is not electrically coupled to the electrical connector, so as to prevent the detection pin from being electrolyzed in the water or in a humid circumstance.

Abstract: Provided is a switched capacitor amplifier capable of outputting a stable output voltage. The switched capacitor amplifier is capable of operating so as to eliminate a charge/discharge time difference between an input capacitor (18) and an output capacitor (19). Accordingly, in a shift from a hold state to a sample state, for example, even if one terminal voltage (V2) of the output capacitor (19) abruptly increases to an output voltage (VOUT), another terminal voltage (Vs) of the output capacitor (19) does not increase abruptly. In other words, an input voltage to an internal amplifier (11) does not increase abruptly. Therefore, an output voltage of the internal amplifier (11) becomes stable and accordingly the output voltage (VOUT) becomes stable as well.

Abstract: Method for setup of parameter values in a RF power amplifier circuit arrangement (200), wherein the amplifier circuit arrangement (200) comprises a first (210) and a second (220) amplification branch and is operated in an out-phasing configuration for amplification of RF input signals with modulated amplitude and modulated phase and respective circuit arrangements are disclosed. According to a first aspect a re-optimization of the dead-time or conversely the duty-cycle, respectively, the phase of the output signal after the combiner can be kept linear with respect to the out-phasing angle. Further, according to a second aspect, additionally to introduction of an optimally chosen dead-time, a non-coherent combiner (Lx, Lx*) can reduce crowbar current and switching losses due the output capacitance (Cds). Furthermore, according to a third aspect the reactive compensation can, additionally or alternatively, be controlled by operating both amplification branches at different duty-cycles.

Abstract: Embodiments provide a configurable low noise amplifier circuit including a gain stage coupled to the input of the low noise amplifier circuit, the low noise amplifier circuit being configurable between one of a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes an impedance matching stage coupled to an input of the configurable low noise amplifier circuit, the output of the impedance matching stage providing an input bias voltage for the impedance matching stage, and a feedback stage coupled to an output of the impedance matching stage and a voltage source, the feedback stage providing a compensated operating voltage for the impedance matching stage.

Abstract: A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.