Abstract: A quadrature amplifier comprises first and second amplifiers, each having an input and an output, a signal splitter connected to the inputs of the two amplifiers, a signal combiner connected to the outputs of the two amplifiers, and an impedance transformer connected to the output of the signal combiner. The signal splitter is a ?3 dB hybrid that splits an input signal into two output signals of equal amplitude that are in phase quadrature. The signal combiner is a ?3 dB hybrid that combines the output signals at the outputs of the two amplifiers. Since the output signals are in phase quadrature, the signals are combined to produce an inphase signal. The impedance transformer matches the output signal to an impedance of approximately 50 Ohms. Capacitive and resistive tuning networks connected to the ports of the signal combiner allow for adjustment of the center frequency and impedance of the signal combiner.

Abstract: Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function.

Abstract: An amplifier includes an envelope detection unit that detects an envelope of a transmission signal; a comparing unit that compares a voltage of the envelope with a reference voltage; a selecting unit that selects, in accordance with a comparison result obtained by the comparing unit, an amplifying element that amplifies the transmission signal from among a plurality of amplifying elements each having different operating power; a voltage control unit that controls, in accordance with the envelope, a voltage that is used to amplify the transmission signal in the amplifying element that is selected by the selecting unit; a current measuring unit that measures a current of a power supply that supplies the voltage that is controlled by the voltage control unit; and a reference voltage control unit that controls the reference voltage such that the current measured by the current measuring unit decreases.

Abstract: First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a first amplifier driving one end of a first speaker through a mechanical switch in a headphone-jack, and a second amplifier driving another end of the first speaker. The second channel bridge amplifier includes third and fourth amplifiers driving respective ends of a second speaker. To suppress click and pop, an amplifier control circuit maintains certain amplifiers (depending on headphone or speaker mode) tri-stated until input coupling capacitors have fully charged and an input signal exceeding a predetermined amount is detected.

Abstract: Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier.

Abstract: Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed.

Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.

Abstract: A differential amplifier comprises a first amplifier (A1) with a signal input (Inp) and a signal output (Out1) that is fed back to a first feedback input (In1) of the first amplifier (A1) and is also connected to a first output (outp) of the differential amplifier. Furthermore, a buffer circuit (Buff) is connected to the first output (outp). A nonlinear resistor circuit (Rnl1, Rnl2) is coupled via a first output node (Vmid1) with the first output (outp) and via a second output node (Vmid2) with the buffer circuit (Buff).

Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device.

Abstract: An electrical receptacle assembly having a housing that includes a wireless transceiver electrically coupled to one or more antennas that can be integrated into the receptacle housing itself or in the receptacle's faceplate. The one or more antennas can be one or more dipoles or a single loop antenna. The housing also houses a power converter that derives its power directly from the line connection to the outlet. A junction box includes an integrated antenna reflector for improved radio direction and propagation relative to the antenna(s). Or, an antenna reflector insert is placed within the junction box behind the electrical receptacle assembly. The electrical receptacle assembly further includes a temperature sensor, a PLC module, or a current/voltage sensor and communicates associated data via its wireless transceiver. A status indicator is disposed on the front of the housing. A reset switch on housing resets the electronics to a default state.

Abstract: A variable gain amplifier includes a plurality of amplification elements arranged to generate amplified representations of an RF input signal at a plurality of nodes. A plurality of controllable response elements each have an input coupled to a different one of the nodes to receive a different one of the amplified representations of the RF input signal. A scale factor generator is coupled to each of the controllable response elements. The scale factor generator receives a gain control signal and generates scale factor signals for varying the response of each of the controllable response elements such that as the scale factor generator sweeps through a full range of the gain control signal, the response of each of the controllable response elements is, in succession, increased smoothly to a peak and thereafter decreased smoothly to a lower level to produce a scaled output.

Abstract: Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function.

Abstract: Techniques are disclosed for canceling an offset component (e.g., dc component or dc offset) in an amplifier circuit. For example, an apparatus comprises an amplifier circuit with an amplifier element and a feedback resistor network coupled between an output of the amplifier element and an input of the amplifier element. The apparatus also comprises a current source coupled to the feedback resistor network, the current source generating a current signal that generates a voltage in a first portion of the feedback resistor network that cancels an offset component present in an input signal received by the amplifier circuit. A second portion of the feedback resistor network may be adjustable so that a gain applied to the input signal is adjustable while the offset component is canceled from the input signal. One or more resistors in the feedback resistor network may be composed of the same or substantially similar material as one or more resistors associated with the current source.

Abstract: A power amplifier, which includes n+1 amplifying units coupled in parallel, where n is an integer greater than or equal to 0, third input ends VR(i) of the n+1 amplifying units are coupled to a power input VL, output ends D(i) of the n+1 amplifying units are coupled to a power input VH, and an output power of the power amplifier is in an increasing function relationship with a capacitance value obtained through accumulation of energy returning capacitors xC of the n+1 amplifying units. The power amplifier changes circuit impedance in a manner of controlling the parallel capacitance value by a switching digital signal, thereby controlling a magnitude of a returned power value and forming different output powers.

Abstract: An amplifying circuit arranged for converting an input signal into an amplified output signal comprising: an input node (11) at an input side of said circuit for receiving said input signal (pi); an output node (9) at an output side of said circuit for outputting said amplified output signal (io); a first gain element (M1) connected between said input and output nodes and provided for converting an input voltage taken from said input signal into a current for forming said amplified output signal; a negative feedback loop (3) over said first gain element, said negative feedback loop having first elements (5, 6) arranged for providing input matching; and a positive feedback loop (2) over said first gain element, said positive feedback loop having second elements (7, 8) arranged for providing additional input matching and gain enhancement of said first gain element.

Abstract: A power amplifier is provided, which includes a power dividing unit, a first power amplification tributary, a second power amplification tributary, and an impedance conversion unit. Input ends of the first power amplification tributary and the second power amplification tributary are coupled to two output ends of the power dividing unit respectively. An output end of the first power amplification tributary is coupled to an output end of the second power amplification tributary through the impedance conversion unit. Rated power of a peak power amplifier in the second power amplification tributary is greater than that of a main power amplifier in the first power amplification tributary. The beneficial effects of the present invention lie in that larger back-off exists at the peak of an efficiency curve of the power amplifier, and in the case that power is back-off, efficiency of the power amplifier is improved.

Abstract: In one embodiment the present invention includes a switching circuit. The circuit comprises a first transistor, a second transistor, and a boost circuit. The first transistor couples a first power source to a first intermediate node during a first phase of operation and the second transistor couples a second intermediate node to the first intermediate node during a second phase of operation. The boost circuit is coupled to the second intermediate node and provides a second power source by a transferring of energy from the first power source. The transferring of energy includes an inductor receiving energy from the first power source during the first phase of operation and providing a portion of said energy to the boost circuit during the second phase of operation. The boost circuit provides a biasing to enable deactivation of the second transistor during the first phase of operation.

Abstract: An amplifier device includes an initial amplifier stage configured to receive a differential input signal at a first leg and a second leg; a final amplifier stage coupled to outputs of the initial amplifier stage, the final amplifier stage including a primary signal amplifier and an error amplifier in each of the first and second legs; and wherein an output of the error amplifier of the first leg is combined with an output of the primary signal amplifier in the second leg, and an output of the error amplifier of the second leg is combined with an output of the primary signal amplifier in the first leg.