Abstract: In described examples, bootstrap diode circuits include a first diode having a first diode input coupled to a voltage supply and a first diode output. Described bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The series-coupled zener diodes are further coupled in parallel with the second diode.

Abstract: A power module including a half bridge circuit having first and second switching elements respectively included in an upper arm and a lower arm thereof, and upper and lower arm drive circuits which respectively drive the first and second switching elements. The power module includes a first ground terminal on a ground side of the second switching element, a second ground terminal connected, via a first ground wiring, to the first ground terminal, a third ground terminal connected, via a second ground wiring including a dumping resistor, to the first ground terminal, a current detection circuit detecting a current flowing through the second switching element, and a control ground switching circuit which performs switching according to a value of the current detected by the current detection circuit, so as to connect a ground terminal of the lower arm drive circuit to the second or third ground terminal.

Abstract: A gate resistance adjustment device has a waveform input unit that inputs waveforms of a drain voltage or a collector voltage and a drain current or a collector current at least one of during a switching device is turned on and during the switching device is turned off, an extraction unit that extracts time required for at least one of turning on or off the switching device and a steady-state drain current or a steady-state collector current of the switching device based on the waveforms input by the waveform input unit, a calculator that calculates a gate resistance of the switching device based on the time and the steady-state drain current or the steady-state collector current that are extracted by the extraction unit, and a setting unit that sets a gate resistance calculated by the calculator in the switching device.

Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

Abstract: A control circuit compatible with battery power supply and external power supply. A first end of a switch module is connected to a power connector module, a second end thereof is connected to a second end of a switch control module, and a third end thereof is connected to an external power supply connector module; the switch module is used for disconnecting a power supply circuit between the battery connector module and the power supply output end when receiving a first control signal, and for connecting the power supply circuit when receiving a second control signal; the switch control module is used for outputting the first or second control signal based on whether an external power supply signal is received; the battery connector module is adapted to be connected to a battery; and the external power supply connector module is adapted to be connected to an external power supply.

Abstract: An isolation transformer and an energy transfer device having an isolation transformer are disclosed. In an embodiments an isolation transformer includes an input winding, an output winding, a third winding, a capacitive element and a resistive element, wherein the capacitive element, the resistive element and the third winding are connected in series, and wherein the input winding, the output winding and the third winding are magnetically coupled.

Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

Abstract: An AC inverter in a vehicle operates using a 24V input when a vehicle powertrain is in a parked/idling state. A first 12V battery is connected with a first bus segment. A second 12V battery is connected with a second bus segment. A switch module selectably interconnects the first and second bus segments. In a nominal 12V state, the batteries are connected in parallel from the bus segments to ground. In a dual voltage state, the batteries are connected in series so the first bus segment is at 12V and the second bus segment is at 24V. A first alternator driven by the powertrain provides a regulated voltage to the second bus segment, wherein the regulated voltage corresponds to 12V when the switch module is in the nominal state and corresponds to 24V when the switch module is in the dual voltage state.

Abstract: A quantum computer comprises an apparatus having atomic objects therein; a first manipulation source configured to provide a first manipulation signal; a second manipulation source configured to provide a second manipulation signal; and a controller. The controller is configured to cause the first manipulation source to provide the first manipulation signal to a region of the apparatus; and cause the second manipulation source to provide the second manipulation signal to the region. The first manipulation signal is tuned to excite atomic objects within the region from a leaked state outside of the qubit space to an intermediary manifold and to suppress excitation of atomic objects that are in the qubit space. The second manipulation signal is tuned to excite atomic objects from the intermediary manifold to a decay manifold from which there is a non-zero probability that an atomic object will decay into the qubit space.

Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Abstract: A switched mode power supply includes a communication interface and an address terminal for setting a communication address for the power supply using the resistance of an external resistor when the external resistor is coupled to the address terminal. The power supply is configured to determine a first resistance value for the external resistor using a first technique, determine a second resistance value for the external resistor using a second technique, set the communication address of the power supply using the first resistance value if the first resistance value is greater than a threshold value, and set the communication address of the power supply using the second resistance value if the first resistance value is less than the threshold value. Other example switched mode power supplies, power systems including one or more power supplies, and methods for setting a communication address of a power supply are also disclosed.

Abstract: In the power transmission unit, a first coil pattern includes first inner side patterns, and first outer side patterns provided on the outer side of the first inner side patterns. A second coil pattern includes second inner side patterns, and second outer side patterns provided on the outer side of the second inner side patterns. The first and second coil patterns are configured such that the first inner side patterns and the second outer side pattern are connected, and the first outer side patterns and the second inner side patterns are connected. Then, the first and second coil patterns transfer power to the power transmission coil pattern of a power receiving unit in a contactless manner.

Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.

Abstract: The disclosure features wireless energy transfer sources that include at least two source resonators and a power source, where: each of the at least two source resonators has a nominal impedance when a device resonator is not positioned on or near any of the at least two source resonators, the nominal impedances of each of the at least two source resonators varying by 10% or less from one another; and the at least two source resonators are configured so that during operation of the wireless energy transfer source, when a device resonator is positioned on or near a first one of the at least two source resonators: (a) the impedance of the first source resonator is reduced to a value smaller than the nominal impedances of each of the other resonators by a factor of 2 or more.

Abstract: A device for phase adjustment preset for an N-path filter comprising a logic block; a ring divider array creating a local oscillator drive for a mixer; the ring divider array comprising: a plurality of registers, each comprising: inputs S, R, D, and clock, and output Q; the plurality of registers comprising at least: a first register; a second register; and an Nth register; a preset control word; wherein the preset control word is applied to the logic block, the logic block providing input to each of the S and the R inputs of each the register; whereby a desired starting phase of the divider is controlled. A method includes defining a desired starting conditions; determining a control word from desired starting conditions; applying control word to logic block; applying a reset signal to logic block; and outputting values for each of S and R to each register.

Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: An electronic circuit includes a first input pin configured to receive a first input signal that includes an enable information and at least one operation parameter information, a second input pin configured to receive a second input signal, an output pin, a control circuit configured to generate a drive signal based on the first input signal and the second input signal, an output circuit configured to generate an output signal at the output pin, the enable information includes an enabled state and a disabled state, the control circuit is configured to generate the drive signal in the enabled state and to turn to the electronic circuit off in the disabled state, the at least one operation parameter information includes information about an operational parameter of the output signal, and the output circuit is configured to use the at least one operation parameter information to change the operational parameter of the output signal.

Abstract: Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

Abstract: In certain embodiments, driver circuitry generates drive signals to drive driven circuitry to transition between first and second states. The driver circuitry has a first-to-second driver circuit that generates a first drive signal to drive the driven circuitry to transition from the first state to the second state and a second-to-first driver circuit that generates a second drive signal to drive the driven circuitry to transition from the second state to the first state. The driver circuitry includes two complementary triggered current pulse generators (described in U.S. Pat. No. 10,554,206) that combine to efficiently provide switch drive for a FET or other reactive load. The triggered drive has fast edges for low switching losses. In certain embodiments, the low power triggered drive circuitry can respond to a slowly changing feedback signal to switch a FET so as to regulate a power converter output.