Abstract: In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common mode noise can decrease the frequency at which these signals are clocked. The use of slots 620 formed in the ground (or power plane) 609 of the substrate and lying perpendicularly (and equally spaced) underneath the differential pair 605 improves the common mode rejection of the differential pair 605 by increasing the common mode impedance without affecting the differential mode impedance. The use of slots 620 does not require modifications to the packaging, and only minor modifications to the substrate.

Abstract: Methods and structures are provided for interleavably processing data signals and error signals in alternating first and second operational phases of successive converter stages of pipelined analog-to-digital converter systems. In particular, converter stages are arranged to interleavably process data signals and error signals in alternating first and second operational phases as they convert input data signals to corresponding digital code. The interleaved methods and structures significantly reduce conversion errors caused by less-than-infinite gain A of converter stage amplifiers. Because this performance enhancement is realized primarily with existing pipelined structure, modification complexity and cost of conventional pipelined systems is substantially reduced. The advantages of the invention are also realized with minimal increase in power consumption and circuit space.

Abstract: A six-drop bus has each driver or receiver terminated at the characteristic impedance of Z0. Each driver or receiver is connected to a segment of transmission line with a characteristic impedance of Z0. Three of these segments are connected at a first point. The other three of these segments are connected at a second point. The first and second points are connected by a central transmission line with a characteristic impedance of Z0/3.

Abstract: A surface acoustic wave filter unit includes three interdigital transducers arranged along the surface acoustic wave propagation direction on a piezoelectric substrate so as to provide a balance-to-unbalance conversion function. Balanced signal terminals are connected to a pair of electrode finger sets of the center interdigital transducer. An unbalanced signal terminal is connected to one electrode finger set of each of the end interdigital transducers. The other electrode finger set of each of the end interdigital transducers is connected to a ground terminal. The ground terminals connected to the end interdigital transducers are electrically isolated from each other on the piezoelectric substrate.

Abstract: A signal coupling apparatus for communication by a medium voltage power line comprises a housing with an inner cavity; an electrode formed on one edge of the housing, one end of the electrode connected to an external medium voltage lead line; a coupling capacitor formed within the cavity and connected to the other end of the electrode; a drain coil formed within the cavity and connected to the coupling capacitor; a power-sided ground terminal formed on one edge of the housing, one end of the ground terminal connected to the drain coil and the other end of the ground terminal connected to a ground terminal of a power system; and a communication-sided connection terminal formed on one edge of the housing, one end of the connection terminal connected to the coupling capacitor and the other end of the connection terminal connected to an external communication equipment.

Abstract: In determining a coding block raster on which a decoded signal is based, a segment of the decoded signal is picked out first, said segment beginning at a certain output sampling value of the decoded signal. Said segment is then converted into a spectral representation, whereupon said spectral representation is then evaluated in relation to a predetermined criterion in order to obtain an evaluation result for the segment. This procedure is repeated for a plurality of different segments beginning at different output sampling values each, in order to obtain a plurality of evaluation results. Finally, the plurality of the evaluation results is searched in order to establish the evaluation result that has an extreme value as compared to the other evaluation results, in such a way that it can be assumed that the segment to which this evaluation result is allocated matches the coding block raster on which the decoded signal is based.

Abstract: A band pass hairpin filter that has improved pass band performance and low loss. The filter has a dielectric substrate. The dielectric substrate has a top and bottom surface. A hairpin resonator is mounted to the top surface. The resonator has an open end and a closed end. An input coupling element is located adjacent to and is communicated with the resonator. An output coupling element is located adjacent to and is communicated with the resonator. A first inductive element is connected to the resonator. A second inductive element is connected to the input coupling element. A third inductive element is connected to the output coupling element.

Abstract: A successive approximation analog-to-digital converter is used for converting an analog input signal into a corresponding digital output signal. The successive approximation analog-to-digital converter has a successive approximation register for storing a first digital bit stream and a second digital bit stream that are related to the analog input signal, and a digital-to-analog converter for generating a first reference voltage and a second reference voltage according to the first and second digital bit streams. The digital-to-analog converter has a first voltage divider and a second voltage divider. The first voltage divider drives the first reference voltage approaching the analog input signal to establish the first digital bit stream, and the second voltage divider drives the second reference voltage approaching the analog input signal to establish the second digital bit stream. Finally, the first and second digital bit streams are averaged to generate the digital output signal.

Abstract: A four-drop bus has each driver or receiver terminated at the characteristic impedance of Z0. Each driver or receiver is connected to a segment of transmission line with a characteristic impedance of Z0. Two of these segments are connected at a first point. The other two of these segments are connected at a second point. The first and second points are connected by a central transmission line with a characteristic impedance of Z0/2.

Abstract: A parallel in serial out (PISO) circuit for converting inputted parallel data bits into a corresponding serial data is disclosed. In the case where the inputted parallel data bits is four, the PISO circuit includes a first latch group, which is provided with four flip-flops, for latching respectively the four data bits at the four flip-flops in synchronism with a clock of 50 MHz. A first selector group is further provided which includes two selectors each of which selectively receives two different data bits latched at the first latch group and each of which outputs sequentially the received two different data bits in synchronism with the clock of 50 MHz. A second latch group, which follows the first selector group, is provided with two flip-flops for latching the two data bits outputted form the two selectors of the first selector group in synchronism with a clock of 100 MHz.

Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: A piezoelectric resonator includes a substrate and a plurality of vibrating portions constructed such that a thin film portion having a piezoelectric thin film of one or more layers is sandwiched by at least a pair of upper electrodes and a lower electrode, which are opposed to each other, on the upper and lower surfaces of the thin film portion. The vibrating portions are separated by at least a distance equal to about &lgr;/2, where &lgr; represents the vibration wavelength, from elements affecting the vibration characteristics.

Abstract: A filter is applied between a digital signal source and a signal receiver for providing compensation of droop caused in a transmission path between the signal source and the signal receiver. The filter provides a high pass characteristic substantially approximating or following in a relevant frequency range an attenuation function substantially proportional to e−k{square root over (f)} or—when denoting attenuation in dB—substantially proportional to the square root of the frequency.

Abstract: An improvement to a conventional multistage pipelined Analog-to-Digital Converter (ADC) 1, the improvement directed to canceling noise resultant from component mismatch. The improved ADC 2 uses in at least a first, and preferably two, stages 21, 22: (i) a flash DAC 212, 222 of a dynamic element matching (DEM) type producing, as well as an associated intermediate analog signal, random bits and parity bits; (ii) a Digital Noise Cancellation (DNC) logic circuit 217, 227, receiving the random bits and the parity bits and a digitized residue sum of the digital output signals arising from all stages beyond a stage of which the DNC logic circuit 217, 227 is a part, so as to produce an error estimate for the stage; and (iii) a subtractor 218, 228 subtracting the error estimates of the DNC logic circuits 217, 227 from the combined digital output signal of all higher stages 22-24 in order to produce a corrected ADC digital output signal.

Abstract: Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “−1” respectively, sum-of-product calculation section 207 multiplies the data output from data conversion section 206 by the demodulated data (soft decision value) stored in demodulated data storage section 201 and then calculates the sum of the products for 1 TTI and stores the sum-of-product result for each data rate, data rate decision section 208 decides the data rate corresponding to a maximum value of the sum-of-product results as the data rate of the demodulated data. This makes it possible to improve the accuracy of data rate decision and reduce decoding errors of a received signal.

Abstract: The present invention is directed at providing methods in a circuit for smoothing transitions relating to a signal processing function. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like, in which the transitions in the signal are smoothed. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: A data transmission system is provided including a clock source, semiconductor integrated circuit devices, a controller configured to control the semiconductor integrated circuit devices, and a clock signal pass connected to the clock source, the controller and the semiconductor integrated circuit devices. The data transmission system may include a daisy chain data pass connected to the controller and the semiconductor integrated circuit devices, and a two-way data strobe signal pass connected to the controller and the semiconductor integrated circuit devices. The clock source, the semiconductor integrated circuit devices and the controller transmit and receive therebetween a clock signal via the clock signal pass. The semiconductor integrated circuit devices and the controller transmit and receive therebetween multi-valued current data via the daisy chain data pass, and a data strobe signal in the form of a binary voltage signal via the two-way data strobe signal pass.

Abstract: The present invention herein describes a tracking analog-to-digital converter, in particular of the differential input type. In an embodiment thereof the tracking analog-to-digital converter, having a differential analog input including a first analog input and a second analog input, and a digital output at a first number of bits comprising: a back and forth counter having a direction input and an output, with a second number of bits; a digital-to-analog converter having a data input coupled to said output of said converter, a reference input and an output, with a second number of bits; a first comparator having a positive input, a negative input coupled to said output of said digital-to-analog converter and an output coupled to said direction input; characterized in that said reference input is coupled to said first analog input and said positive input of said first comparator is coupled to said second analog input.

Abstract: A noise shaper includes a first feedback loop for noise shaping a first feedback signal under normal operating conditions and having a first filter with a first signal transfer function and a second feedback loop that is stable under overload conditions and has a second filter having a second signal transfer function differing from the first signal transfer function. The noise shaper also includes an output circuit block including a quantizer and steering circuitry. The quantizer includes an input simultaneously responsive to outputs of the first and second filters. The steering circuitry steers a feedback from an output of the quantizer to input of the first and second feedback loops. The steering circuitry steers feedback from output of the quantizer to inputs of the first and second feedback loops, the steering circuitry including a first output for providing the first feedback signal to the first feedback loop and a second output for providing a second feedback signal to the second feedback loop.