Abstract: An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the BEOL portion for switching ON/OFF the power to the power isle, (ii) a state recovery circuit comprising a memory element in the FEOL portion or BEOL portion and a transistor configuration in the BEOL portion, and (iii) a wake-up/sleep circuit in the BEOL portion adapted for receiving an identifier. The wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit. Responsive to receiving the identifier, the wake-up/sleep circuit causes the power gating switch to switch OFF/ON the supply power to the power isle and causes the state recovery circuit to store/restore the state of the power isle.

Abstract: The invention introduces a method for data synchronization between a sensor hub and an application processor, which contains at least the following steps: generating and adding a plurality of absolute time stamps in a sensor-data stream; and generating and adding a plurality of pieces of sensor data and a plurality of relative time stamps in the sensor-data stream between the moments of generating each two adjacent absolute time stamps, wherein each relative time stamp is associated with one piece of sensor data.

Abstract: In an embodiment, an apparatus includes an input circuit coupled to a first power supply with a first voltage level, a power circuit coupled to a second power supply with a second voltage level, and an output driver. The input circuit may receive an input signal, and generate an inverted signal dependent upon the input signal. The power circuit may generate a power signal in response to first values of the input and the inverted signals, wherein a voltage level of the power signal may be dependent upon the second voltage level. The power circuit may also generate a third voltage level on the power signal in response to second values of the input and the inverted signals. The output driver may generate an output signal dependent upon the input signal. The output signal may transition between the voltage level of the power signal and the ground reference level.

Abstract: A power conditioning circuit includes at least one power storage device having electrodes coupled for receiving power from a DC power source. At least one active current limit (ACL) circuit coupled to the electrodes of the power storage device is for limiting a maximum power output from the power storage device under fault conditions. A DC-to-DC converter has its inputs coupled to the ACL circuit. At least one crowbar circuit has a first terminal and a second terminal and a shorting device coupled to an output of the DC-to-DC converter for providing output terminals for the power conditioning circuit.

Abstract: Systems and methods are disclosed for determining hours of utility of an application per amount of energy consumed by the application for a wide variety of device types. For each subsystem of a client device, a model of the subsystem is used to estimate a portion of the total energy consumed by the subsystem during a predetermined period of time. Energy consumed by a subsystem is apportioned to one or more applications or daemons that utilize the subsystem. Energy usage by a daemon is apportioned to one or more applications that the daemon performs work on behalf of. A large sample of application energy consumption information is gathered by an energy server and provided to an application information server that is accessible by developers. Thus, a developer can view energy consumption vs. application utility, by client device type and by subsystem for the client device type.

Abstract: Techniques for reducing power consumption of a storage controller are provided. An example method includes determining a back-end bandwidth of a storage system, wherein the back-end of the storage system includes a storage drive communicatively coupled to a storage controller. The method also includes determining a front-end bandwidth of the storage system, wherein the front-end of the storage system includes a front-end bus coupling the storage controller to a host. The method also includes computing a target back-end memory bandwidth based on the back-end bandwidth and computing a target front-end memory bandwidth based on the front-end bandwidth. The method also includes reducing power consumption of the storage controller by reducing a clock frequency of a memory device of the storage controller based on the greater of the target back-end memory bandwidth and the target front-end memory bandwidth.

Abstract: An information processing apparatus according to an exemplary embodiment of the present invention includes a main system and a subsystem. The main system includes a first control unit configured to, before the information processing apparatus shifts to a power-saving state, develop a boot image to be executed by the subsystem in a memory of the subsystem. The subsystem includes a second control unit configured to, in a case where the information processing apparatus returns from the power-saving state, issue an instruction to execute the boot image developed in the memory. The subsystem further includes a third control unit configured to execute the boot image developed in the memory according to the instruction issued by the second control unit.

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract: A solution for synchronizing a network comprising a plurality of interconnected nodes provides a stable synchronized state, especially for large scale networks. Signal transmission speed and the length of each interconnection of the network is configured to cause a delay of the signals received by a node from the other node of the interconnection which is larger than one millionth of the free-running period of the controllable oscillator of the receiving node such that Network-wide synchronization of oscillators is achieved for all nodes of the network in a continuous self-organized process in interaction with the other node of the network.

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract: Systems, methods and products are described that provide accelerated boot performance. One embodiment provides a method including: initiating a booting process of a user operating system of a computer system, wherein the operating system sets a plurality of hardware devices for inclusion in the booting process; identifying a non-critical hardware device in the plurality of hardware devices set for start up according to the user operating system; excluding the non-critical hardware device from the booting process; completing the booting process to provide an operational user operating system to a user without starting an excluded non-critical hardware device; and thereafter loading and initializing the excluded non-critical hardware device as a post-boot task. Other embodiments are described and claimed.

Abstract: There is provided a semiconductor device that can follow a fast voltage change such as a large voltage drop occurring at the time of rapid load fluctuation. The semiconductor device includes a voltage sensor which monitors a power supply voltage at a sampling speed higher than the assumed frequency of power supply voltage fluctuation and outputs a voltage code value, a voltage drop determination circuit which determines, from the voltage code value, that a voltage drop causing a malfunction of a system occurs, and outputs a clock stop signal, and a clock control circuit which controls clock stop, restart, and frequency change.

Abstract: An energy saving device monitors computer activity to determine if the computer is in active use, and if not in active use, it commands the computer to power down to a low energy use power state (and cut power to computer peripherals) unless a user indicates otherwise. The device also communicates the computer's energy usage (as well as energy usage of peripherals) to a remote management center associated with the electricity supply network supplying the computer. When electricity usage needs to be reduced in the electricity supply network, the remote management center sends a demand response event request to the computer, with the request commanding the computer to enter a low energy power use state unless its user indicates otherwise. If the user signifies that the low energy power use state should not be entered, the computer instead enters an intermediate reduced energy use power use state.

Abstract: A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.

Abstract: There is provided a semiconductor device that can follow a fast voltage change such as a large voltage drop occurring at the time of rapid load fluctuation. The semiconductor device includes a voltage sensor which monitors a power supply voltage at a sampling speed higher than the assumed frequency of power supply voltage fluctuation and outputs a voltage code value, a voltage drop determination circuit which determines, from the voltage code value, that a voltage drop causing a malfunction of a system occurs, and outputs a clock stop signal, and a clock control circuit which controls clock stop, restart, and frequency change.

Abstract: A system for drainage avoidance includes an interface and a processor. The interface is configured to receive an indication to power on. A wake up voltage is increased after a power on signal is received. The processor is configured to perform a boot sequence, determine whether the boot sequence completed successfully, and in the event the boot sequence completed successfully, provide a reset indication to reset the wake up voltage.

Abstract: An information processing system includes an operation part that receives an operation performed by a user; and a body part that operates based on a request from the operation part. The operation part includes a power control part that, when receiving a power turning off instruction from the body part, reboots the operation part and causes the operation part to stand by in a power saving state in which some of operations are stopped, and, when receiving a start up notification from the body part, causes the operation part to return from the power saving state.

Abstract: The present technology relates to a control apparatus, a control method, a cable, an electronic apparatus, and a communication apparatus that are capable of increasing the variation of a connection mode of an electronic apparatus to which a predetermined cable such as a USB cable can be connected. An electronic apparatus receiving a baseband signal of a baseband to start initialization processing for causing the electronic apparatus to be in a state of being capable of establishing connection or to turn on or off a power source based on detection results of power of a modulation signal obtained by frequency-converting the baseband signal into a signal of a predetermined frequency band higher than the baseband is controlled. The present technology can be applied to a cable connected to an electronic apparatus to which a cable capable of supplying a power source by bus power such as a USB cable.

Abstract: A control device includes a control unit that controls power supply from a power supply device and a power storage device to an information processing device, and a detection unit that detects power consumption of the information processing device. The control unit controls a value representing the characteristics of an amount of power supplied from the power supply device not to exceed a preset power supply device upper limit value, calculates a record charge and discharge amount representing a record of a past charge and discharge amount of power with respect to the power storage device based on the past power consumption detected by the detection unit, and sets a new power supply device upper limit value based on the record charge and discharge amount.

Abstract: An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.