Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.

Abstract: In some examples, an apparatus can control power provision to a computing device. A controller is to provide power to the computing device from a first power source at a power level above a sustained power rating of the first power source for a first time period, and is to provide power to the computing device from a second power source at a power level above a sustained power rating of the second power source for a second time period after the first time period.

Abstract: A system for controlling electrical power supply of an aircraft includes at least two control boards and at least two switching members. Each switching member is connected to each control board. Each control board includes a processor. Each processor is configured to determine a command for switching states of switch contacts of each switching member and to determine information relating to validity of each switching command. Each switching member includes a transmitter to determine a command to be transmitted to a detector to detect parallelization, a power actuator configured to transmit a power signal to the switch contacts depending on the command received from the detector, and switch contacts configured to selectively open or close an electrical power supply line. The command is selected from the switching commands and the information relating to the validity of each switching command.

Abstract: An information handling system may load first data from a location information area of a first memory, specifying a plurality of locations of metadata for a plurality of stages of basic input/output system (BIOS) initialization. The information handling system may then load first metadata for a first stage of BIOS initialization from a first metadata location of the plurality of locations specified by the first data. The first metadata may contain information for indexing first initialization data located at a first initialization data location. The information handling system may then index the first initialization data of the first initialization data location based, at least in part, on the first metadata. The information handling system may then perform the first stage of BIOS initialization based, at least in part, on the first initialization data.

Abstract: Technologies are described which permit kernel updates or firmware fixes, and include re-initialization of kernel data structures, without losing user context information that has been created by services, virtual machines, or user applications. Tailored code in a server or other computing system sets a kernel soft reset (KSR) indicator and saves the user context to non-volatile storage. When a KSR is underway, boot code skips the power on self-test and similar initializations (thereby reducing downtime), loads a kernel image, initializes kernel data structures, restores the user context, and passes control to the initialized kernel to continue computing system operation with the same user context. Device drivers may also be re-initialized. The loaded kernel may use newly fixed firmware, or may have a security patch installed, for instance. The non-volatile storage may operate at RAM speed, e.g., it may include NVDIMM memory. The kernel may be validated before receiving control.

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Abstract: A first interface performs power delivery and communication with a first external apparatus. A second interface performs power delivery and communication with a second external apparatus. A controller is configured to perform: storing, in a memory, history information relating to power delivery performed with the second external apparatus through the second interface, the history information including identification information of the second external apparatus and an amount of power delivery with the second external apparatus; determining whether to perform a power role switch with the first external apparatus, the power role switch being a switch of a power role between a power source of supplying power and a power sink of receiving power; and in response to determining that the power role switch is to be performed, performing power delivery with the second external apparatus through the second interface based on the history information stored in the memory.

Abstract: Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Abstract: A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Abstract: A data processing system comprising: a host; and a memory system comprising a nonvolatile memory device and a controller suitable for controlling the nonvolatile memory device, wherein the controller comprises: a first reset circuitry suitable for loading firmware from the nonvolatile memory device to a volatile memory, and setting a reset default status; a second reset circuitry suitable for determining whether a reason for a reset request coincides with the reset default status, when the reset request is received from the host, and resetting the memory system; and a firmware load determination circuitry suitable for determining whether to reload the firmware by checking the reset default status.

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract: A computing device includes a power circuit to provide up to a maximum amount of power. The computing device includes internal hardware having an actual current usage power, and ports that are each connectable to a peripheral device having an actual current port usage power. The computing device includes power manager hardware. Responsive to an overpower condition at the power circuit, the computing device is to disconnect a selected port from the power circuit.

Abstract: An SoC device has a boot-code memory that stores boot code and a boot core that accesses the boot-code memory to execute the boot code at startup. The boot core is capable of executing application code after the startup is complete. One or more master cores execute application code. An access control circuit prevents the boot core from accessing the boot-code memory when application code is being executed.

Abstract: A system for drainage avoidance includes an interface and a processor. The interface is configured to receive an indication to power on. The processor is configured to query a wake up voltage threshold, perform a boot sequence, determine whether the boot sequence completed successfully, and in the event the boot sequence completed successfully, provide a reset indication to reset the wake up voltage threshold.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

Abstract: In one or more embodiments, a wireless communications device of an information handling system may receive wireless power from a wireless charging unit, coupled to a wireless docking device; in response to receiving the wireless power from the wireless charging unit, the wireless communications device of the information handling system may establish wireless communications with a wireless communications device of the wireless charging unit; the wireless communications device of the information handling system may wirelessly receive information from the wireless communications device of the wireless charging unit; the wireless communications device of the information handling system may provide the information to an embedded controller of the information handling system; and the embedded controller may perform an action associated with the information handling system.

Abstract: A system and method for partition administrative (admin) targeting in an application server, cloud, or other computing environment. An application server can include one or more partitions, wherein each partition provides an administrative and runtime subdivision of a domain. An administrative virtual target associated with a partition enables an administrator to identify an administrative resource group, including one or more administrative applications or resources, for use with the partition. A partition administrative lifecycle state (e.g., SHUTDOWN) can be associated with various substates (e.g., BOOTED or HALTED). When a partition is associated with a first state or substate (e.g., SHUTDOWN.BOOTED), the administrative resource group in that partition continues to run at an associated target, while other resource groups are shut down. When a partition is associated with a second state or substate (e.g., SHUTDOWN.

Abstract: A power adapter for supplying electrical power to a device includes a processor, an interface for power transfer with the device, a multi-winding feedback converter to receive an AC power input and to convert the AC power input to a DC power output over the interface for the device, and a power conversion control circuit. A voltage level of the DC power output is set based on a reference voltage produced by the processor. The power conversion control circuit receives the reference voltage and a control signal based on the voltage level of the DC power output to generate switch control signals to control switches of the multi-winding feedback converter to control the voltage level of the DC power output. The processor recognizes a load associated with the device and sets, using the reference voltage, the DC power output based on the recognized load.

Abstract: A system and method for deploying a distributed component-based application is disclosed. The system may include a plurality of uniform base components. Each base component of the plurality of uniform base components may host a respective service component, and may include an input port, an output port, a service port, an error, log, and exception port, a monitoring port, and a control port. A first base component may process event messages asynchronously with a second base component and a third base component. The system and method may also support auto-scalability of each base component.

Abstract: A communication device comprising at least one communication port called reception port and another communication port called forward port, each communication port being associated with a respective clock, the communication device being further configured for computing an offset between the respective clocks associated with the reception and forward ports, and synchronizing the respective clocks based on the computed offset.